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Integrated Functions (Continued)

4.5.10 Memory Organization Registers

The GXm processor utilizes a graphics memory aperture

that is up to 4 MB in size. The base address of the graph-

ics memory aperture is stored in the DRAM controller.

The graphics memory is made up of the normal uncom-

pressed frame buffer, compressed display buffer, and cur-

sor buffer. Each buffer begins at a programmable offset

within the graphics memory aperture.

Thevarious memory buffersare arrangedsoastoeffi-

ciently pack the data within the graphics memory aper-

ture. This requires flexibility in the way that the buffers are

arranged when different display modes are in use. The

cursor buffer is a linear block so addressing is straightfor-

ward. The frame buffer and compressed display buffer are

arranged based upon scan lines. Each scan line has a

maximum number of valid or active DWORDs and a delta,

that when added to the previous line offset, points to the

next line. In this way, the buffers may be stored as linear

blocks or as logical blocks as may be desired.

The Memory Organization Registers group consists of six

32-bit

registers

located

GX_BASE+8310h-8328h.

These registers are described below and Table 4-31 gives

their bit formats.

• Display Controller Frame Buffer Start Address

(DC_FB_ST_OFFSET)

- Specifies the offset at which the frame buffer starts.

• Display Controller Compression Buffer Start Address

(DC_CB_ST_OFFSET)

- Specifies the offset at which the compressed display

buffer starts.

• Display Controller Cursor Buffer Start Address

(DC_CURS_ST_OFFSET)

- Specifies the offset at which the cursor memory

buffer starts.

• Display Controller Video Start Address

(DC_VID_ST_OFFSET)

- Specifies the offset at which the video buffer starts.

• Display Controller Line Delta (DC_LINE_DELTA)

- Stores the line delta for the graphics display buffers.

• Display Controller Buffer Size (DC_BUF_SIZE)

- Specifies the number of bytes to transfer for a line of

frame buffer data and the size of the compressed

line buffer. (The compressed line buffer will be invali-

dated if it exceeds the CB_LINE_SIZE, bits [15:9].)

Table 4-31. Display Controller Memory Organization Registers

Bit

Name

Description

GX_BASE+8310h-8313h

DC_FB_ST_OFFSET Register (R/W)

Default Value = xxxxxxxxh

31:22

RSVD

Reserved: Set to 0.

21:0

FB_START

_OFFSET

Frame Buffer Start Offset: This value represents the byte offset of the starting location of the displayed

frame buffer. This value may be changed to achieve panning across a virtual desktop or to allow multiple

buffering.

When this register is programmed to a nonzero value, the compression logic should be disabled. The

memory address defined by bits [21:4] will take effect at the start of the next frame scan. The pixel offset

defined by bits [3:0] will take effect immediately (in general, it should only change during vertical blank-

ing).

GX_BASE+8314h-8317h

DC_CB_ST_OFFSET Register (R/W)

Default Value = xxxxxxxxh

31:22

RSVD

Reserved: Set to 0.

21:0

CB_START

_OFFSET

Compressed Display Buffer Start Offset: This value represents the byte offset of the starting location

of the compressed display buffer. Bits [3:0] should always be programmed to zero so that the start offset

is aligned to a 16-byte boundary. This value should change only when a new display mode is set due to

a change in size of the frame buffer.

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