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Integrated Functions (Continued)

4.5.11 Timing Registers

The GXm processor timing registers control the genera-

tion of sync, blanking, and active display regions. They

provide complete flexibility in interfacing to both CRT and

flat panel displays. These registers will generally be pro-

grammed by the BIOS from an INT 10h call or by the

extended mode driver from a display timing file. Note that

the horizontal timing parameters are specified in character

clocks, which actually means pixels divided by 8, since all

characters are bit mapped. For interlaced display the ver-

tical counter will be incremented twice during each display

line, so vertical timing parameters should be programmed

with reference to the total frame rather than a single field.

The Timing Registers group consists of six 32-bit registers

located at GX_BASE+8330h-834Ch. These registers are

described below and Table 4-32 gives their bit formats.

• Display Controller Horizontal and Total Timing

(DC_H_TIMING_1)

- Contains horizontal active and total timing informa-

tion.

• Display Controller CRT Horizontal Blanking Timing

(DC_H_TIMING_2 Register)

- Contains CRT horizontal blank timing information.

• Display Controller CRT Sync Timing

(DC_H_TIMING_3)

- Contains CRT horizontal sync timing information.

Note,however,thatthis registershould also be

programmed appropriately for flat panel only display

since the horizontal sync transition determines when

to advance the vertical counter.

• Display Controller Flat Panel Horizontal Sync Timing

(DC_FP_H_TIMING)

- Contains horizontal sync timing information for an

attached flat panel display.

• Display Controller Vertical and Total Timing

(DC_V_TIMING_1)

- Contains vertical active and total timing information.

The parameters pertain to both CRT and flat panel

display.

• Display Controller CRT Vertical Blank Timing

(DC_V_TIMING_2)

- Contains vertical blank timing information.

• Display Controller CRT Vertical Sync Timing

(DC_V_TIMING_3)

- Contains CRT vertical sync timing information.

• Display Controller Flat Panel Vertical Sync Timing

(DC_FP_V_TIMING)

- Contains flat panel vertical sync timing information.

Table 4-32. Display Controller Timing Registers

Bit

Name

Description

GX_BASE+8330h-8333h

DC_H_TIMING_1 Register (R/W)

Default Value = xxxxxxxxh

31:27

RSVD

Reserved: Set to 0.

26:19

H_TOTAL

Horizontal Total: This field represents the total number of character clocks for a given scan line

minus 1. Note that the value is necessarily greater than the H_ACTIVE field because it includes bor-

der pixels and blanked pixels. For flat panels, this value will never change. The field [26:16] may be

programmed with the pixel count minus 1, although bits [18:16] are ignored. The horizontal total is

programmable on 8-pixel boundaries only.

18:16

RSVD

Reserved: These bits are readable and writable but have no effect.

15:11

RSVD

Reserved: Set to 0.

10:3

H_ACTIVE

Horizontal Active: This field represents the total number of character clocks for the displayed por-

tion of a scan line minus 1. The field [10:0] may be programmed with the pixel count minus 1,

although bits [2:0] are ignored. The active count is programmable on 8-pixel boundaries only. Note

that for flat panels, if this value is less than the panel active horizontal resolution (H_PANEL), the

parameters H_BLANK_START, H_BLANK_END, H_SYNC_START, and H_SYNC_END should be

reduced by the value of H_ADJUST (or the value of H_PANEL - H_ACTIVE / 2)to achieve horizontal

centering.

2:0

RSVD

Reserved: These bits are readable and writable but have no effect.

Note: Note also that for simultaneous CRT and flat panel display the H_ACTIVE and H_TOTAL parameters pertain to both.

GX_BASE+8334h-8337h

DC_H_TIMING_2 Register (R/W)

Default Value = xxxxxxxxh

31:27

RSVD

Reserved: Set to 0.

26:19

H_BLK_END

Horizontal Blank End: This field represents the character clock count at which the horizontal blank-

ing signal becomes inactive minus 1. The field [26:16] may be programmed with the pixel count

minus 1, although bits [18:16] are ignored. The blank end position is programmable on 8-pixel

boundaries only.

18:16

RSVD

Reserved: These bits are readable and writable but have no effect.

15:11

RSVD

Reserved: Set to 0.

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