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Revision 3.1

Integrated Functions (Continued)

Table 4-40. PCI Configuration Registers

Bit

Name

Description

Index 00h-01h

Vendor Identification Register (RO)

Default Value = 1078h

31:0

VID (RO)

Vendor Identification Register (Read Only): The combination of this value and the device ID uniquely

identifies any PCI device. The Vendor ID is the ID given to national Semiconductor Corporation by the

PCI SIG.

Index 02h-03h

Device Identification Register (RO)

Default Value = 0001h

31:0

DIR (RO)

Device Identification Register (Read Only): This value along with the vendor ID uniquely identifies any

PCI device.

Index 04h-05h

PCI Command Register (R/W)

Default Value = 0007h

15:10

RSVD

Reserved: Set to 0.

9FBE

Fast Back-to-Back Enable: As a master, the GXm processor does not support this function.

This bit returns 0.

8SERR

SERR# Enable: This is used as an output enable gate for the SERR# driver.

7WAT

Wait Cycle Control: GXm processor does not do address/ data stepping.

This bit is always set to 0.

6PE

Parity Error Response:

0 = GXm processor ignores parity errors on the PCI bus.

1 = GXm processor checks for parity errors.

5VPS

VGA Palette Snoop: GXm processor does not support this function.

This bit is always set to 0.

4MS

Memory Write and Invalidate Enable: As a master, the GXm processor does not support this function.

This bit is always set to 0.

3SPC

Special Cycles: GXm processor does not respond to special cycles on the PCI bus.

This bit is always set to 0.

2BM

Bus Master:

0 = GXm processor does not perform master cycles on the PCI.

1 = GXm processor can act as a bus master on the PCI.

1MS

Memory Space: GXm processor will always respond to memory cycles on the PCI.

This bit is always set to 1.

0IOS

I/O Space: GXm processor will not respond to I/O accesses from the PCI.

This bit is always set to 1.

Index 06h-07h

PCI Device Status Register (RO, R/W Clear)

Default Value = 0280h

DPE

Detected Parity Error: When a parity error is detected, this bit is set to 1.

This bit can be cleared to 0 by writing a 1 to it.

SSE

Signaled System Error: This bit is set whenever SERR# is driven active.

RMA

Received Master Abort: This bit is set whenever a master abort cycle occurs. A master abort will occur

whenever a PCI cycle is not claimed except for special cycles.

This bit can be cleared to 0 by writing a 1 to it.

RTA

Received Target Abort: This bit is set whenever a target abort is received while the GXm processor is

master of the cycle.

This bit can be cleared to 0 by writing a 1 to it.

STA

Signaled Target Abort: This bit is set whenever the GXm processor signals a target abort. A target

abort is signaled when an address parity occurs for an address that hits in the GXm processor’s address

space.

This bit can be cleared to 0 by writing a 1 to it.

10:9

Devise Timing:

00 = Fast

01 = Medium

10 = Slow

11 = Reserved

The GXm processor performs medium DEVSEL# active for addresses that hit into the GXm processor

address space. These two bits are always set to 01.

GXM Datasheet(PDF) 158 Page - National Semiconductor (TI)

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