GXM datasheet(159/244 Pages) NSC

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Integrated Functions (Continued)

8DPD

Data Parity Detected: This bit is set when three conditions are met.

1) GXm processor asserted PERR# or observed PERR# asserted;

2) GXm processor is the master for the cycle in which the PERR# occurred; and

3) PE (bit 6 of Command Register) is enabled.

This bit can be cleared to 0 by writing a 1 to it.

7FBS

Fast Back-to-Back Capable: As a target, the processor is capable of accepting Fast Back-to-Back

transactions.

This bit is always set to 1.

6:0

RSVD

Reserved: Set to 0.

Index 08h

Revision Identification Register (RO)

Default Value = 00h

7:0

RID (RO)

Revision ID (Read Only): This register contains the revision number of the GXm design.

Index 09h-0Bh

Class Code Register (RO)

Default Value = 060000h

23:16

CLASS

Class Code: The class code register is used to identify the generic function of the device. The

GXm processor is classified as a host bridge device (06).

15:0

RSVD (RO)

Reserved (Read Only)

Index 0Ch

Cache Line Size Register (RO)

Default Value = 00h

7:0

CACHELINE

Cache Line Size (Read Only): The cache line size register specifies the system cacheline size in units

of 32-bit words. This function is not supported in the GXm processor.

Index 0Dh

Latency Timer Register (R/W)

Default Value = 00h

7:5

RSVD

Reserved: Set to 0.

4:0

LAT_TIMER

Latency Timer: The latency timer as used in this implementation will prevent a system lockup resulting

from a slave the does not responded to the master. If the register value is set to 00h, the timer is dis-

abled. Otherwise, Timer represents the 5 MSBs of an 8-bit counter. The counter will reset on each valid

data transfer. If the counter expires before the next TRDY# is received active, then the slave is consid-

ered to be incapable of responding, and the master will stop the transaction with a master abort and flag

an SERR# active. This would also keep the master from being retried forever by a slave device that con-

tinues to issue retries. In these cases, the master will also stop the cycle with a master abort.

Index 0Eh-3Fh

Reserved

Default Value = 00h

Index 40h

PCI Control Function 1 Register (R/W)

Default Value = 00h

7RSVD

Reserved: Set to 0.

6SW

Single Write Mode: PCI slave supports:

0 = Multiple PCI write cycles

1 = Single cycle write transfers on the PCI bus. The slave will perform a target disconnect with the first

data transferred.

5SR

Single Read Mode: PCI slave supports:

0 = Multiple PCI read cycles.

1 = Single cycle read transfers on the PCI bus. The slave will perform a target disconnect with the first

data transferred.

4RXBNE

Force Retry when X-Bus Buffers are Not Empty:

0 = PCI slave accepts the PCI cycle with data in the PCI master write buffers. The data in the PCI master

write buffers will not be affected or corrupted. The PCI master holds request active indicating the need to

access the PCI bus.

1 = PCI slave retries cycles if the PCI master X-bus write buffers contain buffered data.

3SWBE

PCI Slave Write Buffer Enable: PCI slave write buffers: 0 = Disable; 1 = Enable.

2CLRE

PCI Cache Line Read Enable: Read operations from the PCI into the GXm processor:

0 = Single cycle unless a read multiple or memory read line command is used.

1 = Cause a cache line read to occur.

1XBE

X-Bus Burst Enable: PCI slave acting as a master performs burst cycles on the X-bus on write-back

invalidate cycles from the PCI. 0 = Disable; 1 = Enable.

(This bit does not control read bursting; bit 2 does.)

0RSVD

Reserved: Should return a value of 0.

Table 4-40. PCI Configuration Registers (Continued)

Bit

Name

Description

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