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Virtual Subsystem Architecture (Continued)

A VGA is made up of several functional units.

•The frame buffer is 256 KB of memory that provides

data for the video display. It is organized as 64 K 32-bit

DWORDs.

•The sequencer decomposes word and DWORD CPU

accesses into byte operations for the graphics

controller. It also controls a number of miscellaneous

functions, including reset and some clocking controls.

•The graphics controller provides most of the interface

between CPU data and the frame buffer. It allows the

programmer to read and write frame buffer data in

different formats. Plus provides ROP (raster operation)

and masking functions.

•The CRT controller provides video timing signals and

address generation for video refresh. It also provides a

text cursor.

•The attribute controller contains the video refresh

datapath, including text rasterization and palette

lookup.

•The general registers provide status information for

the programmer as well as control over VGA-host

address mapping and clock selection. This is all

handled in hardware by the graphics pipeline.

It is important to understand that a VGA is constructed of

numerous independent functions. Most of the register

fields correspond to controls that were originally built out

of discrete logic or were part of a dedicated controller

such as the 6845. The notion of a VGA “mode” is a higher-

level convention to denote a particular set of values for the

registers. Many popular programs do not use standard

modes, preferring instead to produce their own VGA set-

ups that are optimal for their purposes.

5.1.1.1

VGA Memory Organization

TheVGA memory is organizedas64K 32-bit DWORDs.

This organization is usually presented as four 64 KB

“planes”. A plane consists of one byte out of every

DWORD. Thus, plane 0 refers to the least significant byte

from every one of the 64 K DWORDs. The addressing

granularity of this memory is a DWORD, not a byte; that is,

consecutive addresses refer to consecutive DWORDs.

The only provision for byte-granularity addressing is the

four-byte enable signals used for writes. In C parlance,

single_plane_byte = (dword_fb[address] >>

(plane * 8)) & 0xFF;

When dealing with VGA, it is important to recognize the

distinction

between

host

addresses,

frame

buffer

addresses, and the refresh address pipe. A VGA control-

ler contains lots of hardware to translate between these

address spaces in different ways, and understanding

these translations is critical to understanding the entire

device. In standard four-plane graphics modes, a frame-

buffer DWORD provides eight 4-bit pixels. The left-most

pixel comes from bit 7 of each plane, with plane 3 provid-

ing the most significant bit.

pixel[i].bit[j] = dword_fb[address].bit[j*8 + (7-i)]

5.1.1.2

VGA Front End

The VGA front end consists of address and data transla-

tions between the CPU and the frame buffer. This func-

tionality is contained within the graphics controller and

sequencer components. Most of the front end functionality

is implemented in the VGA read and write hardware of the

GXm processor. An important axiom of the VGA is that

the front end and back end are controlled independently.

There are no register fields that control the behavior of

both pieces. Terms like “VGA odd/even mode” are there-

fore somewhat misleading; there are two different controls

for odd/even functionality in the front end, and two sepa-

rate controls in the refresh path to cause “sensible”

refresh behavior for frame buffer contents written in

odd/even mode. Normally, all these fields would be set up

together, but they don’t have to be. This sort of orthogonal

behavior gives rise to the enormous number of possible

VGA “modes”. The CPU end of the read and write pipes is

one byte wide. Word and DWORD accesses from the

Table 5-1. Standard VGA Modes

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