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Revision 3.1

Power Management (Continued)

Table 6-2. Power Management Control and Status Registers

Bit

Name

Description

GX_BASE+8500h-8503h

PM_STAT_SMI Register (R/W)

Default Value = xxxxxx00h

31:8

RSVD

Reserved — These bits are not used. Do not write to these bits.

7:3

RSVD

Reserved — Set to 0.

2SMI_MEM

SMI VGA Emulation Memory — This bit is set high if a SMI was generated for VGA emulation in

response to a VGA memory access. An SMI can be generated on a memory access to one of three

regions in the A0000h-to-BFFFFh range as specified in the BC_XMAP_1 register.

1SMI_IO

SMI VGA Emulation I/O — This bit is set high if a SMI was generated for VGA emulation in

response to an I/O access. An SMI can be generated on a I/O access to one of three regions in the

3B0h-to-3DFh range as specified in the BC_XMAP_1 register.

0SMI_PIN

SMI Pin — When set high, this bit indicates that the SMI# input pin has been asserted to the

GXm processor.

Note: These bits are “sticky” bits and can only be cleared with a write of ‘1’ to the respective bit.

GX_BASE+8504h-8507h

PM_CNTRL_TEN Register (R/W)

Default Value = xxxxxx00h

31:8

RSVD

Reserved — These bits are not used. Do not write to these bits.

7:6

RSVD

Reserved — Set to 0.

5X_TEST (WO)

Transmission Test (Write Only) — Setting this bit causes the GXm processor to immediately trans-

mit the current contents of the serial packet. This bit is write only and is used primarily for test. This

bit returns 0 on a read.

4:3

X_FREQ

Transmission Frequency — This field indicates the time between serial packet transmissions.

Serial packet transmissions occur at the selected interval only if at least one of the packet bits is set

high: 00 = Disable transmitter; 01 = 1 ms; 10 = 5 ms; 11 = 10 ms.

2CPU_RD

CPU Activity Read Enable — Setting this bit high enables reporting of CPU Level-1 cache read

misses that are not a result of an instruction fetch. This bit is a don’t-care if the CMEN bit is not set

high

1CPU_EN

CPU Activity Master Enable — Setting this bit high enables reporting of CPU Level-1 cache

misses in bit 6 of the serial transmission packet. When enabled, the CPU Level-1 cache miss activity

is reported on any read (assuming the CREN is set high) or write access excluding misses that

resulted from an instruction fetch.

0VID_EN

Video Event Enable — Setting this bit high enables video decode events to be reported in bit 0 of

the serial transmission packet. CPU or graphics-pipeline accesses to the graphics memory and dis-

play-controller-register accesses are also reported.

GX_BASE+8508h-850Bh

PM_CNTRL_CSTP Register (R/W)

Default Value = xxxxxx00h

31:8

RSVD

Reserved — These bits are not used. Do not write to these bits.

7:1

RSVD

Reserved — Set to 0.

0CLK_STP

Clock Stop — This bit configures the GXm processor for Suspend Refresh Mode or 3-Volt Suspend

Mode:

0 = Suspend Refresh Mode. The clocks to the memory and display controller are active.

1 = 3-Volt Suspend Mode. All internal clocks are stopped.

Note: When this register is set high and the Suspend input pin (SUSP#) is asserted, the GXm processor stops all it’s internal clocks,

and asserts the Suspend Acknowledge output pin (SUSPA#). Once SUSPA# is asserted the GXm processor’s SYSCLK input

can be stopped. If this register is cleared, the internal memory-controller and display-controller clocks are not stopped on the

SUSP#/SUSPA# sequence, and the SYSCLK input can not be stopped.

GX_BASE+850Ch-850Fh

PM_SER_PACK Register (R/W)

Default Value = xxxxxx00h

31:8

RSVD

Reserved — These bits are not used. Do not write to these bits.

7VID_IRQ

Video IRQ — This bit indicates the occurrence of a video vertical sync pulse. This bit is set at the

same timer that the VINT (Vertical Interrupt) bit is set in the DC_TIMING_CFG register. The VINT bit

has a corresponding enable bit (VIEN) in the DC_TIM_CFG register.

6CPU_ACT

CPU Activity — This bit indicates the occurrence of a level 1 cache miss that was not a result of an

instruction fetch. This bit has a corresponding enable bit in the PM_CNTL_TEN register.

5:2

RSVD

Reserved — Set to 0.

1USR_DEF

Programmable Address Decode — This bit indicates the occurrence of a programmable memory

address decode. This bit is set based on the values of the PM_BASE register and the PM_MASK

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