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Power Management (Continued)

0VID_DEC

Video Decode — This bit indicates that the CPU has accessed either the Display Controller regis-

ters or the graphics memory region. This bit has a corresponding enable bit in the

PM_CNTRL_TEN.

Note: The GXm processor transmits the contents of the serial packet only when a bit in the packet register is set and the interval

counter has elapsed. The CS5530 decodes the serial packet after each transmission. Once a bit in the packet is set, it will

remain set until the completion of the next packet transmission. Successive events of the same type that occur between packet

transmissions are ignored. Multiple unique events between packet transmissions will accumulate in this register.

Table 6-2. Power Management Control and Status Registers (Continued)

Bit

Name

Description

Table 6-3. Power Management Programmable Address Region Registers

Bit

Name

Description

Index FFFFFF6Ch

PM_BASE Register (R/W)

Default Value = 0000000h

31:28

RSVD

Reserved — Set to 0.

27:2

BASE_ADDR

Base Address — This is the word-aligned base address for the programmable memory range com-

pare. The actual address range is determined with this field and the PM_MASK register value.

1:0

RSVD

Reserved — Set to 0.

Index FFFFFF7Ch

PM_MASK Register (R/W)

Default Value = 0000000h

31:28

RSVD

Reserved — Set to 0.

27:2

ADR_MASK

Address Mask — This field is the address mask for the BASE_ADDR field in the PM_BASE regis-

ter. If a bit in the ADR_MASK field is cleared the corresponding bit in the BASE_ADDR field must

match the processor address. If a bit in the mask field is set high, the corresponding bit in the

BASE_ADDR field always compares. If the processor cycle type matches the values of the WE and

RE bits, and all bits in the BADD field match the processor address based on the ADR_MASK field,

bit 1 will be set high in the serial transmission packet.

1WE

Write Enable — Compare memory write cycles with BASE_ADDR and ADR_MASK:

0 = Disable; 1 = Enable.

0RE

Read Enable — Compare memory read cycles with BASE_ADDR and ADR_MASK:

0 = Disable; 1 = Enable

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