DA7212 datasheet(49/129 Pages) DIALOG

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DA7212

Ultra-low power stereo codec

Company confidential

Datasheet

Revision 3c

24-Nov-2015

49 of 129

13.26.1 Normal PLL mode (DAI master)

The DA7212 contains a Phase Locked Loop (PLL) that can be used to generate the required

11.2896 MHz or 12.288 MHz internal system clock when a frequency of between 2 and 50 MHz is

applied to MCLK. This allows sharing of clocks between devices in an application, reducing total

system cost. For example, the codec may operate from common 13 MHz or 19.2 MHz system clock

frequency.

The PLL is enabled by asserting PLL_EN. Once the PLL is enabled and has achieved phase lock,

PLL bypass mode is disabled, and the output of the PLL is used as the system clock.

The PLL input divider register (PLL_INDIV) is used to reduce the PLL reference frequency to the

usable range of 2 to 50 MHz as shown in Table 35 reduces the PLL reference frequency according to

the following equation:

FREF = FMCLK ÷ (2^PLL_INDIV)

Table 35: PLL input divider

MCLK input frequency (MHz)

Input divider, (÷N)

PLL_INDIV register (0x27 [3:2])

– 10

÷2

– 20

÷4

– 40

÷8

– 50

÷16

The value of the PLL feedback divider is used to set the voltage controlled oscillator (VCO) frequency

to 8 times the required system clock frequency (see Table 34).

FVCO = FREF × PLL feedback divider

The value of the PLL feedback divider is an unsigned number in the range of 0 to 128. It consists of

seven integer bits and 13 fractional bits split across three registers:

● PLL_INTEGER holds the seven integer bits

● PLL_FRAC_TOP holds the top bits (MSB) of the fractional part of the divisor

● PLL_FRAC_BOT holds the bottom bits (LSB) of the fractional part of the divisor

DA7212 Datasheet(PDF) 49 Page - Dialog Semiconductor