DA7212 datasheet(4/129 Pages) DIALOG

4 / 129 page

DA7212

Ultra-low power stereo codec

Company confidential

Datasheet

Revision 3c

24-Nov-2015

4 of 129

16 Ordering information ................................................................................................................ 119

Applications information ........................................................................................... 120

Appendix A

A.1

Codec initialisation ............................................................................................................ 120

A.2

Automatic ALC calibration................................................................................................. 120

A.3

Troubleshooting ................................................................................................................ 121

Components................................................................................................................ 122

Appendix B

B.1

Audio inputs ...................................................................................................................... 122

B.2

Microphone bias ................................................................................................................ 123

B.3

Digital microphone ............................................................................................................ 123

B.4

Audio outputs .................................................................................................................... 123

B.5

Headphone charge pump ................................................................................................. 124

B.6

Digital interfaces................................................................................................................ 125

B.7

References ........................................................................................................................ 126

B.8

Supplies ............................................................................................................................ 126

B.9

Ground .............................................................................................................................. 127

B.10 Capacitor selection............................................................................................................ 127

PCB layout guidelines ............................................................................................... 128

Appendix C

C.1

Layout and schematic support .......................................................................................... 128

C.2

General recommendations................................................................................................ 128

Figures

Figure 1: The DA7212 chip.................................................................................................................... 1

Figure 2: Block diagram showing component values for a typical application ...................................... 8

Figure 3: DA7212 ball layout ................................................................................................................. 9

Figure 4: I2C bus timing ...................................................................................................................... 24

Figure 5: Digital audio interface timing diagram .................................................................................. 25

Figure 6: Audio input routing and gain ranges .................................................................................... 28

Figure 7: Typical microphone application for MIC1 (MIC2 is similar).................................................. 29

Figure 8: Digital microphone timing example ...................................................................................... 30

Figure 9: Principle of operation of the ALC ......................................................................................... 32

Figure 10: Attack, delay and hold parameters..................................................................................... 33

Figure 11: Analogue output signal paths and gain ranges .................................................................. 35

Figure 12: Input (clk) and output clocks (cp_clk and cp_clk2) at CP_FCONTROL = 010 .................. 39

Figure 13: ADC and DAC DC blocking (Cut-

off frequency setting ‘00’ to ‘11’, 16 kHz) ...................... 42

Figure 14: Wind noise high-pass filter (cut-

off frequency setting ‘000’ to ‘111’, 16 kHz) .................... 43

Figure 15: Equaliser filter band 1 frequency response at FS = 48 kHz............................................... 44

Figure 16: Equaliser filter band 2 frequency response at FS = 48 kHz............................................... 45

Figure 17: Equaliser filter band 3 frequency response at FS = 48 kHz............................................... 45

Figure 18: Equaliser filter band 4 frequency response at FS = 48 kHz............................................... 45

Figure 19: Equaliser filter band 5 frequency response at FS = 48 kHz............................................... 46

Figure 20: Schematic of the I2C control interface bus ........................................................................ 52

Figure 21 Timing of I2C START and STOP conditions ....................................................................... 53

Figure 22: I2C byte write (SDA signal) ................................................................................................ 53

Figure 23: Examples of the I2C byte read (SDA line) ......................................................................... 53

Figure 24: Examples of I2C page read (SDA line) .............................................................................. 54

Figure 25: I2C page write (SDA line)................................................................................................... 54

Figure 26: I2C repeated write (SDA line) ............................................................................................ 54

Figure 27: Master mode (DAI_CLK_EN = 1)....................................................................................... 55

Figure 28: Slave mode (DAI_CLK_EN = 0)......................................................................................... 55

Figure 29: I2S mode ............................................................................................................................ 56

Figure 30: Left justified mode .............................................................................................................. 56

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