DA7212 datasheet(3/129 Pages) DIALOG

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DA7212

Ultra-low power stereo codec

Company confidential

Datasheet

Revision 3c

24-Nov-2015

3 of 129

13.17.2

Specifying clock frequencies when tracking the charge pump output demand... 40

13.17.3

Controlling the boost of the charge pump clock-frequency ................................. 40

13.17.3.1

CP_ANALOGUE_LVL = 01 ............................................................. 40

13.17.3.2

CP_ANALOGUE_LVL = 10 ............................................................. 40

13.18 Other charge pump controls ............................................................................................... 41

13.19 Digital signal processing engine ......................................................................................... 42

13.20 Variable high-pass audio filter (DC Cut) ............................................................................. 42

13.21 Variable high pass filter (wind noise filtering) ..................................................................... 43

13.22 DAC 5-band equaliser......................................................................................................... 44

13.23 Soft mute ............................................................................................................................. 46

13.24 Playback noise-gate............................................................................................................ 46

13.25 Clock modes ....................................................................................................................... 47

13.26 PLL bypass mode ............................................................................................................... 48

13.26.1

Normal PLL mode (DAI master) .......................................................................... 49

13.26.2

Example calculation of the feedback divider setting:........................................... 50

13.27 SRM PLL mode (DAI slave) ................................................................................................ 51

13.28 32 kHz PLL mode (DAI master) .......................................................................................... 51

13.29 Operating with a 2 MHz to 5 MHz MCLK ............................................................................ 51

13.30 Mixed sample rates ............................................................................................................. 51

13.31 I2C control interface ............................................................................................................ 52

13.32 Details of the I2C control interface protocol ........................................................................ 53

13.33 Digital audio interface (DAI) ................................................................................................ 55

13.34 I2S mode ............................................................................................................................. 56

13.35 Left justified mode ............................................................................................................... 56

13.36 Right justified mode............................................................................................................. 56

13.37 DSP mode ........................................................................................................................... 57

13.38 Time division multiplexing (TDM) mode.............................................................................. 58

13.38.1

Configuration of the digital audio interface .......................................................... 59

13.39 Pop-free and click-free start-up using the system controllers............................................. 59

13.39.1

Level 1 system controller (SCL1) ........................................................................ 59

13.39.2

Level 2 system controller (SCL2) ........................................................................ 60

13.40 Power supply

– standby mode............................................................................................ 60

13.40.1

Entering standby mode........................................................................................ 60

13.40.2

Exiting standby mode .......................................................................................... 60

14 Register definitions ..................................................................................................................... 61

14.1 Register map....................................................................................................................... 61

14.2 Status registers ................................................................................................................... 67

14.3 System initialisation registers.............................................................................................. 72

14.4 Input gain/select filter registers ........................................................................................... 78

14.5 Output gain-filter registers................................................................................................... 83

14.6 System controller registers.................................................................................................. 91

14.7 Control registers .................................................................................................................. 93

14.8 Mixed sample mode registers ........................................................................................... 102

14.9 Configuration registers ...................................................................................................... 103

15 Package information ................................................................................................................. 118

15.1 Package outlines ............................................................................................................... 118

15.2 Soldering information ........................................................................................................ 119

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