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AGC Theory of Operation

A block diagram of the AGC is shown in Figure 34. The

DVGA interface comprises four pins for each of the channels.

The first three pins of this interface are a 3-bit binary word

that controls the DVGA gain in 6dB steps (AGAIN). The final

pin is ASTROBE which allows the AGAIN bits to be latched

into the DVGA’s register. A key feature of the ASTROBE,

illustrated Figure 35, is that it toggles only if the data on

AGAIN has changed from the previous cycle. Not shown is

that ASTROBE and BSTROBE are independent. For exam-

ple, ASTROBE only toggles when AGAIN has changed.

BSTROBE will not toggle because AGAIN has changed.

This is done to minimize unnecessary digital noise on the

sensitive analog path through the DVGA. ASTROBE and

BSTROBE are asserted during MR and SI to properly initial-

ize the DVGAs.

The absolute value circuit and the 2-stage, decimate-by-8

CIC filter comprise the power detection part of the AGC. The

The absolute value circuit doubles the effective input fre-

quency. This has the effect of reducing the power detector

For a full-scale sinusoidal input, the absolute value circuit

output is a dc value of

. Because the absolute

value circuit also generates undesired even harmonic terms,

the CIC filter (response shown in Figure 36), is required to,

remove these harmonics. The first response null occurs at

circuit is about 10dB below the dc this means that the ripple

in the detected level is about 0.7dB or less for input frequen-

AGC_COMB_ORD register to either 1 or 2 will narrow the

power detector’s bandwidth as shown in Figure 36.

The “FIXED TO FLOAT CONVERTER” takes the fixed point

9-bit output from the CIC filter and converts it to a “floating

point” number. This conversion is done so that the 32 values

in the RAM can be uniformly assigned (dB scale) to detected

power levels (54 dB range). This provides a resolution of

1.7dB between detected power levels. The truth table for this

converter is given in Table 3. The upper three bits of the out-

put represent the exponent (e) and the lower 2 are the man-

tissa (m). The exponent is determined by the position of the

AGC_LOOP_GAIN

10

16

5

8

12

12

AGC_HOLD_IC

-REF

LOG

FUNCTION PROGRAMMED

INTO RAM

AGC_IC_A

3

AIN[13:4]

9

AGC_TABLE

AGAIN

Figure 34. CLC5903 AGC circuit, Channel A

EXP

(from MUXA)

9

Figure 35. Timing diagram for AGC/DVGA interface, Channel A. Refer to Figure 9 for detailed timing information.

ASTROBE

AGAIN[2:0]

CK

CK/8

ASTROBE does not pulse because AGAIN[2:0] does not change

511

2

π

⁄

()

⋅

Figure 36. Power detector filter response, 52MHz

0

5

10

15

20

25

30

35

40

45

50

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

10

Frequency/MHz

AGC Power Detection Filter: Amplitude Response

CIC

CIC + 1−tap Comb

CIC + 4−tap Comb

AGC_COMB_ORD=2

AGC_COMB_ORD=0

AGC_COMB_ORD=1