CLC5903 datasheet(14/29 Pages) NSC

14 / 29 page

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The 2’s complement format represents full-scale negative as

10000000 and full-scale positive as 01111111 for an 8-bit

example.

The 16 bit phase offset is set by loading the PHASE register

according to the formula PHASE = 216P/2

π, where P is the

desired phase in radians ranging between 0 and 2

π. PHASE

is an unsigned 16-bit number. P ranges from 0 to 2

π(1-2-16).

Phase dithering can be enabled to reduce the spurious sig-

nals created by the NCO due to phase truncation. This trun-

cation is unavoidable since the frequency resolution is much

finer than the phase resolution. With dither enabled, spurs

due to phase truncation are below -100 dBc for all frequen-

cies and phase offsets. Each NCO has its own dither source

and the initial state of one is maximally offset with respect to

the other so that they are effectively uncorrelated. The phase

dither sources are on by default. They are independently

controlled by the DITH_A and DITH_B bits. The amplitude

resolution of the ROM creates a worst-case spur amplitude

of -101dBc rendering amplitude dither unnecessary.

The spectrum plots in Figure 17 show the effectiveness of

phase dither in reducing NCO spurs due to phase truncation

for a worst-case example (just below FS/8). With dither off,

the spur is at -86.4dBFS. With dither on, the spur is below

-125dBFS, disappearing into the noise floor. This spur is

spread into the noise floor which results in an SNR of

-83.6dBFS. The channel filter’s processing gain will further

improve the SNR.

Figure 18 shows the spur levels as the tuning frequency is

scanned over a narrow portion of the frequency range. The

spurs are again a result of phase quantization but their loca-

tions move about as the frequency scan progresses. As

before, the peak spur level drops when dithering is enabled.

When dither is enabled and the fundamental frequency is

exactly at FS/8, the worst-case spur due to amplitude quanti-

zation can be observed at -101dBc in Figure 19.

Four Stage CIC Filter

The mixer outputs are decimated by a factor of N in a four

stage CIC filter. N is programmable to any integer between 8

and 2048. Decimation is programmed in the DEC register

where DEC = N - 1. The programmable decimation allows

the chip’s usable output bandwidth to range from about

2.6kHz to 1.3MHz when the input data rate (which is equal to

the chip’s clock rate, FCK) is 52 MHz. For the maximum sam-

ple rate of 78MHz, the CLC5903’s output bandwidth will

range from about 4.76kHz to 1.95MHz. A block diagram of

the CIC filter is shown in Figure 20.

The CIC filter is primarily used to decimate the high-rate

incoming data while providing a rough lowpass characteris-

tic. The lowpass filter will have a sin(x)/x response (similar to

the AGC’s CIC shown in Figure 36 on page 24) where the

first null is at FS/N.

The CIC filter has a gain equal to N4 (filter decimation^4)

which must be compensated for in the “SHIFT UP” circuit

shown in Figure 20 as well as Figure 16. This circuit has a

gain equal to 2(SCALE-44), where SCALE ranges from 0 to 40.

This circuit divides the input signal by 244 providing maxi-

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-160

-140

-120

-100

-80

-60

-40

-20

Frequency Normalized to FS

Figure 18. NCO Spurs due to Phase Quantization

Complex NCO Output

Phase Dither Disabled

N C O f r eq ue nc y sw ep t

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-160

-140

-120

-100

-80

-60

-40

-20

Frequency Normalized to FS

Figure 19. Worst Case Amplitude Spur, NCO at FS/8

Complex NCO Output

Phase Dither Enabled

DATA

OUT

SCALE

Figure 20. Four-stage decimate by N CIC filter

Data @ FCK

= FS (FSAMPLE)

Data @ FCK/N

N = DEC + 1

22-bit input to SHIFT_UP is aligned

at the bottom of the 66-bit path when SCALE=0.

Detailed Description (Continued)

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