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CS5376A Datasheet(PDF) 74 Page - Cirrus Logic |
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CS5376A Datasheet(HTML) 74 Page - Cirrus Logic |
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74 / 107 page  CS5376A 74 In SPI mode 3, the SCK2 serial clock is defined ini- tially in a high state. Output data on the SO pin is invalid until the initial falling edge of SCK2, and the first rising edge of SCK2 latches valid data. SPI modes 1 and 4 work similarly to modes 0 and 3, with the serial clock defined to have data valid on falling edges and transitioning on rising edges. Figure 40. SPI 2 Master Mode Transactions SO 0x02 ADDR Data1 SI SO SI SPI 2 Write to External Slave SPI 2 Read from External Slave Data3 Data2 0x03 ADDR Data1 Data3 Data2 CS CS SPI2CMD[15:8] SPI2CMD[7:0] SPI2DAT SPI2CMD[15:8] SPI2CMD[7:0] SPI2DAT Instruction Opcode Address Definition Write 0x02 SPI2CMD[7:0] Write serial peripheral beginning at the address given in SPI2CMD[7:0]. Read 0x03 SPI2CMD[7:0] Read serial peripheral beginning at the address given in SPI2CMD[7:0]. |
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