DS1680

7 of 23

CLOCK, CALENDAR, AND ALARM

The time and calendar information is accessed by reading/writing the appropriate register bytes. Note that

some bits are set to zero. These bits will always read zero regardless of how they are written. Also note

that registers 0Eh to 7Fh are reserved. These registers will always read zero regardless of how they are

written. The contents of the time, calendar, and alarm registers are in the binary-coded decimal (BCD)

format.

The DS1680 can run in either 12- hour or 24- hour mode. Bit 6 of the hours register is defined as the 12- or

24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the

AM/PM bit with logic one being PM. In the 24- hour mode, bit 5 is the second 10- hour bit (20–23 hours).

The DS1680 also contains a time-of-day alarm. The alarm registers are located in registers 07h to 0Ah.

Bit 7 of each of the alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, an

alarm will occur once per week when the values stored in time-keeping registers 00h to 03h match the

values stored in the time-of-day alarm registers. An alarm will be generated every day when mask bit of

the day alarm register is set to one. An alarm will be generated every hour when the day and hour alarm

mask bits are set to one. Similarly, an alarm will be generated every minute when the day, hour, and

minute alarm mask bits are set to one. When day, hour, minute, and second alarm mask bits are set to one,

an alarm will occur every second.

TIME-OF-DAY ALARM BITS Table 1

ALARM REGISTER MASK BITS (BIT 7)

Seconds

Minutes

Hours

Day

1

1

1

1

Alarm once per second.

0

1

1

1

Alarm when seconds match.

0

0

1

1

Alarm when minutes and seconds match.

0

0

0

1

Alarm when hours, minutes and seconds match.

0

0

0

0

Alarm when day, hours, minutes and seconds match.

SPECIAL PURPOSE REGISTERS

The DS1680 has two additional registers (control register and status register) that control the RTC and

interrupts.

CONTROL REGISTER – 0Bh

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

EOSC

WP

SP1

SP0

0

0

0

AIE

EOSC (Enable Oscillator) – This bit, when set to logic 0, will start the oscillator. When this bit is set to

SP0 and SP1 (Speed Select) – These bits select the on time of the X- and Y- measurement duty cycle.

The programmable duty cycle section has more detail.

WP (Write Protect) – Before any write operation to the RTC or any other registers, this bit must be logic

0. When high, the write-protect bit prevents a write operation to any register.