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DS3134 Datasheet(PDF) 77 Page - Dallas Semiconductor |
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DS3134 Datasheet(HTML) 77 Page - Dallas Semiconductor |
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77 / 203 page  DS3134 77 of 203 Register Name: BERTEC1 Register Description: BERT 24-Bit Error Counter (upper) Register Address: 051Ch 76 5432 10 BERT 24-Bit Error Counter 15 14 13 12 11 10 9 8 BERT 24-Bit Error Counter (upper byte) Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0. Bits 0 to 15 / BERT 24-Bit Error Counter (BEC). Upper two words of the 24-bit error counter. This 24-bit counter will increment for each data bit received in error. This counter is not disabled when the receive BERT loses synchronization. This counter will be loaded with the current bit count value when the LC control bit in the BERTC0 register is toggled from a low (0) to a high (1). When full, this counter will saturate and set the BECO status bit. |
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