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DS3134 Datasheet(PDF) 100 Page - Dallas Semiconductor

Part # DS3134
Description  Chateau Channelized T1 And E1 And HDLC Controller
PDF  203 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3134 Datasheet(HTML) 100 Page - Dallas Semiconductor

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Receive DMA Actions
A typical scenario for the Receive DMA is as follows:
1. The receive DMA gets a request from the Receive FIFO that it has packet data that needs to be sent to
the PCI Bus.
2. The receive DMA determines whether the incoming packet data should be stored in a large buffer or a
small buffer.
3. The receive DMA then reads a Free Queue Descriptor (either by reading a single descriptor or a burst
of descriptors) indicating where in main memory there exists some free data buffer space and where
the associated free Packet Descriptor resides.
4. The receive DMA starts storing packet data in the previously free buffer data space by writing it out
through the PCI Bus.
5. When the receive DMA realizes that the current data buffer is filled (by knowing the buffer size it can
calculate this), it then reads another Free Queue Descriptor to find another free data buffer and Packet
Descriptor location.
6. The receive DMA then writes the previous Packet Descriptor and creates a linked list by placing the
current descriptor in the Next Descriptor Pointer field and then it starts filling the new buffer location.
Figure 8.1.1A provides an example of Packet Descriptors being link listed together (see Channel 2).
7. This continues to all of the packet data is stored.
8. The receive DMA will either wait until a packet has been completely received or until a
programmable number (from 1 to 7) of data buffers have been filled before writing the Done Queue
Descriptor which indicates to the Host that packet data is ready for processing.
Host Actions
The Host will typically handle the receive DMA as follows:
1. The Host is always trying to make available free data buffer space and hence it tries to fill the Free
Queue Descriptor.
2. The Host will either poll or be interrupted that some incoming packet data is ready for processing.
3. The Host then reads the Done Queue Descriptor circular queue to find out which channel has data
available, what the status is, and where the receive Packet Descriptor is located.
4. The Host then reads the receive Packet Descriptor and begins processing the data.
5. The Host then reads the Next Descriptor Pointer in the link listed chain and continues this process
until either a number (from 1 to 7) of descriptors have been processed or an end of packet has been
reached.
6. The Host then checks the Done Queue Descriptor circular queue to see if any more data buffers are
ready for processing.



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