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DS3134 Datasheet(PDF) 105 Page - Dallas Semiconductor

Part # DS3134
Description  Chateau Channelized T1 And E1 And HDLC Controller
PDF  203 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3134 Datasheet(HTML) 105 Page - Dallas Semiconductor

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8.1.3 FREE QUEUE
The Host will write to the Receive Free Queue, the 32-bit addresses of the available (i.e. free) data buffers
and their associated Packet Descriptors. The descriptor space is indicated via a 16-bit pointer which the
DMA will use along with the Receive Packet Descriptor Base Address to find the exact 32-bit address of
the associated Receive Packet Descriptor.
Receive Free Queue Descriptor Figure 8.1.3A
dword 0
Free Data Buffer Address (32)
dword 1
Unused (16)
Free Packet Descriptor Pointer (16)
Note: The organization of the Free Queue is not affected by the enabling of Big Endian
dword 0; Bits 0 to 31 / Data Buffer Address. Direct 32-bit starting address of a free data buffer.
dword 1; Bits 0 to 15 / Free Packet Descriptor Pointer. This 16-bit value is the offset from the
Receive Descriptor Base Address of the free descriptor space associated with the free data buffer in dword
0. Note: This is an index not an absolute address.
dword 1; Bits 16 to 31 / Unused. Not used by the DMA. Can be set to any value by the Host and will
be ignored by the Receive DMA.
The Receive DMA will read from the Receive Free Queue Descriptor circular queue which data buffers
and their associated descriptors are available for use by the DMA.
The Receive Free Queue Descriptor is actually a set of two circular queues. See Figure 8.1.3B. There is
one circular queue that indicates where free large buffers and their associated free descriptors exist and
there is another circular queue that indicates where free small buffers and their associated free descriptors
exist.
Large and Small Buffer Size Handling
Via the Receive Configuration RAM Buffer Size field, the DMA knows for a particular HDLC channel,
whether the incoming packets should be stored in the large or the small free data buffers. The Host
informs the DMA of the size of both the large and small buffers via the Receive Large and Small Buffer
Size (RLBS/RSBS) registers. For example, when the DMA knows that data is ready to be written onto
the PCI Bus, it checks to see if the data is to be sent to a large buffer or a small buffer and then it goes to
the appropriate Free Queue Descriptor and pulls the next available free buffer address and free descriptor
pointer. If the Host wishes to have only one buffer size, then the Receive Free Queue Small Buffer Start
Address will be set equal to the Receive Free Queue End Address and in the Receive Configuration
RAM, none of the active HDLC channels will be configured for the small buffer size.
To keep track of the addresses of the dual circular queues in the Receive Free Queue, there are a set of
internal addresses within the device that are accessed by both the Host and the DMA. On initialization,
the Host will configure all of the registers shown in Table 8.1.3B. After initialization, the DMA will only
write to (i.e. change) the read pointers and the Host will only write to the write pointers.



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