DS3134 datasheet(191/203 Pages) DALLAS

Part #	DS3134

Description	Chateau Channelized T1 And E1 And HDLC Controller

PDF	203 Pages

Scroll/Zoom	100%

Manufacturer	DALLAS [Dallas Semiconductor]

Direct Link	https://www.maximintegrated.com/en.html

Logo

191 / 203 page

DS3134

191 of 203

LAYER ONE PORT AC TIMING DIAGRAM Figure 12A

Note:

TC and RC are independent from each other. In the above timing diagram, all the signals started with “T”

are reference to the transmit clock TC and all the signals started with “R” are reference to the receive

clock RC.

AC CHARACTERISTICS - LOCAL BUS IN BRIDGE MODE (LMS = 0)

°C TO +70°C; VDD = 3.0V TO 3.6V)

Parameter

Symbol

Min

Typ

Max

Units

Notes

Delay Time from the Rising Edge of

LCLK to Output Valid from Tri-State

Delay Time from the Rising Edge of

LCLK to Tri-State from Output Valid

Delay Time from the Rising Edge of

LCLK to Output Valid from an

Already Active Drive State

LD[15:0] Set Up Time to the Rising

Edge of LCLK

LD[15:0] Hold Time from the Rising

Edge of LCLK

Input Set Up Time to the Rising Edge

of LCLK

Input Hold Time from the Rising

Edge of LCLK

RC[n] / TC[n]

Normal Mode

RD[n] / RS[n] /

TS[n]

TD[n]

RC[n] / TC[n]

Inverted Mode

l1 ac

DS3134 Datasheet(PDF) 191 Page - Dallas Semiconductor