DP7132

7

Doc No. MD-2124, Rev. E

© NIDEC COPAL ELECTRONICS CORP.

Characteristics subject to change without notice

Figure 4. Acknowledge Condition

SERIAL BUS PROTOCOL

The following defines the features of the 2-wire bus

protocol:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes

in the data line while the clock is high will be

interpreted as a START or STOP condition.

The device controlling the transfer is a master, typically

a processor or controller, and the device being controlled

is the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the DP7132 will be considered

a slave device in all applications.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The DP7132 monitors the

SDA and SCL lines and will not respond until this

condition is met (see Fig. 3).

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition (see Fig. 3).

Figure 3. Start/Stop Condition

Acknowledge

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data (see Fig. 4).

The DP7132 responds with an acknowledge after

receiving a START condition and its slave address. If

the device has been selected along with a write operation,

it responds with an acknowledge after receiving each

8-bit byte.

When the DP7132 is in a READ mode it transmits 8 bits

of data, releases the SDA line, and monitors the line for

an acknowledge. Once it receives this acknowledge,

the DP7132 will continue to transmit data. If no

acknowledge is sent by the Master, the device terminates

data transmission and waits for a STOP condition.

Acknowledge Polling

The disabling of the inputs can be used to take advantage

of the typical write cycle time. Once the STOP condition

is issued to indicate the end of the write operation, the

DP7132 initiates the internal write cycle. ACK polling

can be initiated immediately. This involves issuing the

START condition followed by the slave address. If the

DP7132 is still busy with the write operation, no ACK

will be returned. If the DP7132 has completed the write

operation, an ACK will be returned and the host can then

proceed with the next instruction operation.

START

CONDITION

STOP

CONDITION

SDA

SCL

9

8

1

START

SCL FROM

MASTER

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DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK DELAY ( tAA)

ACK SETUP ( tSU:DAT)