DP7132

5

Doc No. MD-2124, Rev. E

© NIDEC COPAL ELECTRONICS CORP.

Characteristics subject to change without notice

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DP TIMING

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WRITE CYCLE LIMITS

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.

During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not

respond to its slave address.

RELIABILITY CHARACTERISTICS

Notes:

1.

This parameter is tested initially and after a design or process change that affects the parameter.

2.

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TYPICAL PERFORMANCE CHARACTERISTICS

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163248648096

112

128

Tap position

Vcc=2.7V; V+=8v

Vcc=5.5V; V+=16V

Icc2 (NV write) vs Temperature

0

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-50 -30 -10 10

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90 110 130

Temperature (°C)

Vcc = 2.7V

Vcc = 5.5V