DP7132

8

Doc. No. MD-2124, Rev. E

© NIDEC COPAL ELECTRONICS CORP.

Characteristics subject to change without notice

Figure 5. Access Register Addressing Using 3 Bytes

Table 2. Byte 1 Slave Address and Instruction Byte

h

2

0

-

s

s

e

r

d

d

a

Rn

o

Ai

t

c

e

l

e

s

)

h

0

0

(

R

D

/

)

h

0

8

(

R

WC

T

S

0

1

0

1

0

00

0

A

00

0

0

0

0

1

0

A

1

0

0

0

0

0

0

0

A

T

S

0

1

0

1

0

00

0

A

00

0

0

0

0

1

0

A

0

0

0

0

0

0

0

0

A

P

S

e

t

y

b

d

r

3

e

t

y

b

d

n

2

e

t

y

b

t

s

1

SP

Table 1. Access Control Register

DEVICE DESCRIPTION

Access Control Register

The volatile register WCR and the non-volatile register

DR are accessed only by addressing the volatile Access

and write operations (see Table 1). The first byte is the

slave address/instruction byte (see details below). The

second byte contains the address (02h) of the AR

register. The data in the third byte controls which register

WCR (80h) or DR (00h) is being addressed (see Figure

5).

Slave Address Instruction Byte Description

The first byte sent to the DP7132 from the master

processor is called the Slave/DP Address Byte. The

most significant five bits of the slave address are a

device type identifier. For the DP7132 these bits are

fixed at 01010 (refer to Table 2).

The next two bits, A1 and A0, are the internal slave

address and must match the physical device address

which is defined by the state of the A1 and A0 input pins.

Only the device with slave address matching the input

byte will be accessed by the master. This allows up to 4

devices to reside on the same bus. The A1 and A0 inputs

can be actively driven by CMOS input signals or tied to

The last bit is the READ/WRITE bit and determines the

function to be performed. If it is a “1” a read command is

initiated and if it is a “0” a write is initiated. For the AR

register only write is allowed.

After the Master sends a START condition and the slave

address byte, the DP7132 monitors the bus and

responds with an acknowledge when its address matches

the transmitted slave address.

SLAVE

ADDRESS

& INSTRUCTION

S

A

C

K

A

C

K

S

T

O

P

P

BUS ACTIVITY:

MASTER

SDA LINE

S

T

A

R

T

A

C

K

FIXED

VARIABLE

AR REGISTER

ADDRESS

WCR/DR

SELECTION

r

e

i

f

i

t

n

e

d

I

e

p

y

T

e

c

i

v

es

Ds

e

r

d

d

A

e

v

a

l/

Sd

a

e

R

e

t

i

r

W

4

D

I3

D

I2

D

I1

D

I0

D

I1

A0

A/

R

W

01

01

0

X

X

X

)

B

S

M

(

)

B

S

L

(