AX5051 datasheet(13/28 Pages) ONSEMI

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AX5051

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CIRCUIT DESCRIPTION

The AX5051 is a true single chip low−power CMOS

transceiver primarily for use in SRD bands. The on−chip

transceiver consists of a fully integrated RF front−end with

modulator, and demodulator. Base band data processing is

implemented in an advanced and flexible communication

controller that enables user−friendly communication via the

SPI interface.

AX5051 can be operated from 2.2 V to 3.6 V power

supply over a temperature range from −40

°C to 85°C, it

consumes 11 − 45 mA for transmitting depending on the

output power, 19 mA for receiving in high sensitivity mode

and 18 mA for receiving in low power mode.

The AX5051 features make it an ideal interface for

integration into various battery powered SRD solutions such

as ticketing or as transceiver for telemetric applications e.g.

in sensors. As primary application, the transceiver is

intended for UHF radio equipment in accordance with the

European Telecommunication Standard Institute (ETSI)

specification EN 300 220−1 and the US Federal

Communications Commission (FCC) standard CFR47, part

15. The use of AX5051 in accordance to FCC Par 15.247,

allows for improved range in the 915 MHz band.

Additionally AX5051 is compatible with the low frequency

standards of 802.15.4 (ZigBee). It therefore incorporates a

DSSS engine, which spreads data on the transmitter and

despreads data for the receiver. Spreading and despreading

is possible on all data rates and modulation schemes. The net

transfer rate is reduced by a factor of 15 in this case. For

802.15.4 either 600 or 300 kbps modes have to be chosen.

The AX5051 sends and receives data via the SPI port in

frames. This standard operation mode is called Frame Mode.

Pre and post ambles as well as checksums can be generated

automatically. Interrupts control the data flow between a

controller and the AX5051.

The AX5051 behaves as a SPI slave interface.

Configuration of the AX5051 is also done via the SPI

interface.

AX5051 supports any data rate from 1 kbps to 350 kbps

for FSK and MSK and from 1 kbps for 600 kbps for ASK and

10 kbps to 600 kbps PSK. To achieve optimum performance

for specific data rates and modulation schemes several

are outlined in the following, for details see the AX5051

Programming Manual.

The receiver supports multi−channel operation for all data

rates and modulation schemes.

Voltage Regulator

The AX5051 uses an on−chip voltage regulator to create

a stable supply voltage for the internal circuitry at pin VREG

from the primary supply VDD_IO. All VDD pins of the

device must be connected to VREG. The antenna pins

ANTP and ANTN must be DC biased to VREG. The I/O

level of the digital pins is VDD_IO.

The voltage regulator requires a 1

mF low ESR capacitor

at pin VREG.

In power−down mode the voltage regulator typically

outputs 1.7 V at VREG, if it is powered−up its output rises

to typically 2.5 V. At device power−up the regulator is in

power−down mode.

The voltage regulator must be powered−up before receive

or transmit operations can be initiated. This is handled

automatically when programming the device modes via the

PWRMODE register.

check if the regulated voltage is above 1.3 V or 2.3 V, sticky

versions of the bits are provided that can be used to detect

low power events (brown−out detection).

Crystal Oscillator

The on−chip crystal oscillator allows the use of an

inexpensive quartz crystal as the RF generation subsystem’s

timing reference. Although a wider range of crystal

frequencies can be handled by the crystal oscillator circuit,

it is recommended to use 16 MHz as reference frequency for

ASK and PSK modulations independent of the data rate. For

FSK it is recommended to use a 16 MHz crystal for data rates

below 200 kbps and 24 MHz for data rates above 200 kbps.

The oscillator circuit is enabled by programming the

PWRMODE register. At power−up it is not enabled.

To adjust the circuit’s characteristics to the quartz crystal

being used without using additional external components,

both the transconductance and the tuning capacitance of the

crystal oscillator can be programmed.

The transconductance is programmed via register bits

XTALOSCGM[3:0] in register XTALOSC.

The integrated programmable tuning capacitor bank

makes it possible to connect the oscillator directly to pins

CLK16N and CLK16P without the need for external

capacitors. It is programmed using bits XTALCAP[5:0] in

To synchronize the receiver frequency to a carrier signal,

the oscillator frequency could be tuned using the capacitor

bank however, the recommended method to implement

frequency synchronization is to make use of the high

resolution RF frequency generation sub−system together

with the Automatic Frequency Control, both are described

further down.

Alternatively a single ended reference (TXCO, CXO)

may be used. The CMOS levels should be applied to

CLK16P via an AC coupling with the crystal oscillator

enabled.

SYSCLK Output

The SYSCLK pin outputs the reference clock signal

divided by a programmable integer. Divisions from 1 to

2048 are possible. For divider ratios > 1 the duty cycle is

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