AX5051 datasheet(16/28 Pages) ONSEMI

16 / 28 page

AX5051

www.onsemi.com

transitions for the demodulator bit timing recovery, and

makes sure that the transmitted spectrum does not have

discrete lines even if the transmitted data is cyclic. It

does so without adding additional bits, i.e. without

changing the data rate. Spectral Shaping uses a

self−synchronizing feedback shift register.

The encoder is programmed using the register

ENCODING, details and recommendations on usage are

given in the AX5051 Programming Manual.

Framing and FIFO

Most radio systems today group data into packets. The

framing unit is responsible for converting these packets into

a bit−stream suitable for the modulator, and to extract

packets from the continuous bit−stream arriving from the

demodulator.

The Framing unit supports four different modes:

• HDLC

• Raw

• Raw with Preamble Match

• 802.15.4 Compliant

The micro−controller communicates with the framing

unit through a 4 level

× 10 bit FIFO. The FIFO decouples

micro−controller timing from the radio (modulator and

demodulator) timing. The bottom 8 bits of the FIFO contain

transmit or receive data. The top 2 bit are used to convey

meta information in HDLC and 802.15.4 modes. They are

unused in Raw and Raw with Preamble Match modes. The

meta information consists of packet begin / end information

and the result of CRC checks.

The AX5051 contains one FIFO. Its direction is switched

depending on whether transmit or receive mode is selected.

The FIFO can be operated in polled or interrupt driven

modes. In polled mode, the micro−controller must

periodically read the FIFO status register or the FIFO count

In interrupt mode EMPTY, NOT EMPTY, FULL, NOT

FULL and programmable level interrupts are provided. The

AX5051 signals interrupts by asserting (driving high) its

IRQ line. The interrupt line is level triggered, active high.

Interrupts are acknowledged by removing the cause for the

interrupt, i.e. by emptying or filling the FIFO.

Basic FIFO status (EMPTY, FULL, Overrun, Under−run,

and the top two bits of the top FIFO word) are also provided

during each SPI access on MISO while the micro−controller

shifts out the register address on MOSI. See the SPI interface

section for details. This feature significantly reduces the

number of SPI accesses necessary during transmit and

receive.

HDLC Mode

NOTE: HDLC mode follows High−Level Data Link

Control (HDLC, ISO 13239) protocol.

HDLC Mode is the main framing mode of the AX5051. In

this mode, the AX5051 performs automatic packet

delimiting, and optional packet correctness check by

inserting and checking a cyclic redundancy check (CRC)

field.

The packet structure is given in the following table.

Table 14.

Flag

Address

Control

Information

FCS

(Optional Flag)

8 bit

8 or 16 bit

Variable length, 0 or more bits in multiples of 8

16 / 32 bit

8 bit

HDLC packets are delimited with flag sequences of

content 0x7E.

In AX5051 the meaning of address and control is user

defined. The Frame Check Sequence (FCS) can be

programmed to be CRC−CCITT, CRC−16 or CRC−32.

The receiver checks the CRC, the result can be retrieved

from the FIFO, the CRC is appended to the received data.

For details on implementing a HDLC communication see

the AX5051 Programming Manual.

Raw Mode

In Raw mode, the AX5051 does not perform any packet

delimiting or byte synchronization. It simply serializes

transmit bytes and de−serializes the received bit−stream and

groups it into bytes.

This mode is ideal for implementing legacy protocols in

software.

Raw Mode with Preamble Match

Raw mode with preamble match is similar to raw mode.

In this mode, however, the receiver does not receive

anything until it detects a user programmable bit pattern

(called the preamble) in the receive bit−stream. When it

detects the preamble, it aligns the de−serialization to it.

The preamble can be between 4 and 32 bits long.

802.15.4 (ZigBee) DSSS

802.15.4 uses binary phase shift keying (PSK) with

300 kbit/s (868 MHz band) or 600 kbit/s (915 MHz band) on

the radio. The usable bit rate is only a 15th of the radio bit

rate, however. A spreading function in the transmitter

expands the user bit rate by a factor of 15, to make the

transmission more robust. The despreader function of the

receiver undoes that.

In 802.15.4 mode, the AX5051 framing unit performs the

spreading and despreading function according to the

802.15.4 specification. In receive mode, the framing unit

will also automatically search for the 802.15.4 preamble,

meaning that no interrupts will have to be serviced by the

micro−controller until a packet start is detected.

AX5051 Datasheet(PDF) 16 Page - ON Semiconductor

AX5051 Datasheet(HTML) 16 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL