AX5051

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18

Table 17. PWRMODE REGISTER

PWRMODE Register

Typical Idd

Description

Name

0101

STANDBY

The crystal oscillator is powered on; receiver and transmitter are off.

650 mA

1000

SYNTHRX

The synthesizer is running on the receive frequency. Transmitter and

receiver are still off. This mode is used to let the synthesizer settle on the

correct frequency for receive.

11 mA

1001

FULLRX

Synthesizer and receiver are running.

17 − 19 mA

1100

SYNTHTX

The synthesizer is running on the transmit frequency. Transmitter and

receiver are still off. This mode is used to let the synthesizer settle on the

correct frequency for transmit.

10 mA

1101

FULLTX

Synthesizer and transmitter are running. Do not switch into this mode

before the synthesizer has completely settled on the transmit frequency (in

SYNTHTX mode), otherwise spurious spectral transmissions will occur.

11 − 45 mA

Table 18. A TYPICAL PWRMODE SEQUENCE FOR A TRANSMIT SESSION

Step

PWRMODE

Remarks

1

POWERDOWN

2

STANDBY

The settling time is dominated by the crystal used, typical value 3 ms.

3

SYNTHTX

The synthesizer settling time is 5 – 50 ms depending on settings, see section AC Characteristics

4

FULLTX

Data transmission

5

SYNTHTX

This step must be programmed after FULLTX mode, or the device will not enter

POWERDOWN or STANDBY mode.

6

POWERDOWN

Table 19. A TYPICAL PWRMODE SEQUENCE FOR A RECEIVE SESSION

Step

PWRMODE [3:0]

Remarks

1

POWERDOWN

2

STANDBY

The settling time is dominated by the crystal used, typical value 3 ms.

3

SYNTHRX

The synthesizer settling time is 5 – 50 ms depending on settings, see section AC Characteristics

4

FULLRX

Data reception

5

POWERDOWN

Serial Peripheral Interface

The AX5051 can be programmed via a four wire serial

interface according SPI using the pins CLK, MOSI, MISO

and SEL. Registers for setting up the AX5051 are

programmed via the serial peripheral interface in all device

modes.

When the interface signal SEL is pulled low, a 16−bit

configuration data stream is expected on the input signal pin

MOSI, which is interpreted as D0...D7, A0...A6, R_N/W.

Data read from the interface appears on MISO.

Figure 3 shows a write/read access to the interface. The

data stream is built of an address byte including read/write

information and a data byte. Depending on the R_N/W bit

and address bits A[6..0], data D[7..0] can be written via

MOSI or read at the pin MISO.

R_N/W = 0 means read mode, R_N/W = 1 means write

mode.

The read sequence starts with 7 bits of status information

S[6..0] followed by 8 data bits.

The status bits contain the following information:

Table 20.

S6

S5

S4

S3

S2

S1

S0

PLL LOCK

FIFO OVER

FIFO UNDER

FIFO FULL

FIFO EMPTY

FIFOSTAT(1)

FIFOSTAT(0)