MIC24045 datasheet(19/46 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005568A-page 19

MIC24045

4.3

Enable (EN)

The EN pin starts/stops the power delivery to the out-

put. It does not turn off the internal LDO. The EN pin

does not act as a Reset signal for the I2C registers, only

the VDDA UVLO circuit does.

Rising threshold is a precise 1.21V±70 mV. A 135 mV

typical hysteresis prevents chattering due to switching

noise and/or slow edges. A 2 µA typical pull-down cur-

rent with ±1 µA accuracy prevents unwanted start-ups

if the EN pin is momentarily floating. To achieve auto-

matic turn-on as soon as enough voltage is present,

connect EN to VDDA.

4.4

Power Good (PG)

PG is an open-drain output. For asserting a logic HIGH

level, PG requires an external resistor connected to a

pull-up voltage (VPU_PG), which should not exceed

5.5V.

PG is asserted with a typical delay of 0.45 ms when the

output voltage (OUTSNS) reaches 92.5% of its target

regulation voltage. PG is de-asserted with a typical

delay of 80 µs when the output voltage falls below 90%

of its target regulation voltage. The PG falling delay

acts as a de-glitch timer against very short spikes. The

PG output is always immediately de-asserted when the

EN pin is below the power delivery enable threshold

(EN_R/EN_F). The pull-up resistor should be large

enough to limit the PG pin current to below 2 mA. The

PG is in a defined state once the VDDA voltage is

greater than about 1V, but with reduced current sinking

capability.

The PG is also immediately de-asserted (with no delay)

whenever an undervoltage condition on VDDA is

detected, or in thermal shutdown.

4.5

Inductor (LX) and Bootstrap (BST)

The external inductor is connected to LX. The high-side

MOSFET driver circuit is powered between BST and

LX by means of an external capacitor (typically 100 nF)

that is replenished from rail VDDP during the low-side

MOSFET ON-time. The bootstrap diode is internal.

4.6

Output Sensing (OUTSNS) and

Compensation (COMP)

OUTSNS should be connected exactly to the desired

point-of-load regulation, avoiding parasitic resistive

drops. The impedance seen into OUTSNS is high (tens

of k

 or more, depending on the selected output volt-

age value), therefore its loading effect is typically neg-

ligible. OUTSNS is also used by the slope

compensation generator.

COMP is the connection for the external compensation

network. COMP is driven by the output of the transcon-

ductance error amplifier. Care must be taken to return

the compensation network ground directly to AGND.

4.7

Soft-Start

The MIC24045 features four different I2C-selectable

soft-start slew-rate values (0.16V/ms, 0.38V/ms,

0.76V/ms and 1.5V/ms). See the section Section 5.0

“Registers Maps and I2C Programmability”

for the

value vs. code mapping. The internal reference is

ramped up at the selected rate. Note that this is the

internal reference soft-start slew rate and that the

actual slew rate seen at the output should take into

account the internal divider attenuation, as detailed in

the Section 7.0 “Application Information”.

4.8

Start-Up Delay

The MIC24045 features eight different I2C-selectable

start-up delays (from 0 ms to 10 ms). These represent

the added delays from the EN rising edge to the begin-

ning of the power delivery (soft-start). See the section

Section 5.0, Registers Maps and I2C Programma-

bility

for the value vs. code mapping.

4.9

Switching Frequency

The MIC24045 features eight different I2C-selectable

switching frequencies from 310 kHz to 1200 kHz. See

Section 5.0 “Registers Maps and I2C Programma-

bility”

for the value vs. code mapping. Also pay atten-

tion to voltage conversion ratio limitations due to

minimum TON and TOFF, as stated in Section 7.0

“Application Information”

4.10

Pre-Biased Output Start-Up

The MIC24045 is designed to achieve safe start-up into

a pre-biased output without discharging the output

capacitors.

4.11

Thermal Warning and Thermal

Shutdown

The MIC24045 has a thermal shutdown protection that

prevents operation at excessive temperature. The ther-

mal shutdown threshold is typically set at +160°C with

a hysteresis of +25°C.

The MIC24045 features a Thermal Warning flag that is

readable through the I2C interface (register polling is

needed). The Thermal Warning flag signals the

approaching of thermal shutdown, so that appropriate

system-level countermeasures can be undertaken.

Note that a thermal shutdown event will not disable the

internal VDDA linear regulator, but only the power stage.

In this way, the I2C interface remains powered and can

still be read throughout the duration of the thermal shut-

down.

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