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ADPD103 Datasheet(PDF) 4 Page - Analog Devices |
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ADPD103 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 53 page  Data Sheet ADPD103 Rev. B | Page 3 of 52 FUNCTIONAL BLOCK DIAGRAM LED3 DRIVER LED2 DRIVER ANALOG BLOCK TIME SLOT A DATA TIME SLOT B DATA DIGITAL DATAPATH AND INTERFACE CONTROL LED3 LEVEL AND TIMING CONTROL LED2 LEVEL AND TIMING CONTROL LED1 DRIVER LED1 LEVEL AND TIMING CONTROL SDA SCL INT DGND AGND VREF 1µF AVDD DVDD ADPD103 14-BIT ADC TIA TIA TIA TIA AFE: SIGNAL CONDITIONING AFE: SIGNAL CONDITIONING AFE: SIGNAL CONDITIONING AFE: SIGNAL CONDITIONING PDC TIME SLOT SWITCH PD1 PD8 PD5 PD2 PD6 PD3 PD7 PD4 LEDX1 LEDX2 LEDX3 LGND VLED PDSO LED1 LED2 LED3 VBIAS BPF ±1 INTEGRATOR VBIAS BPF ±1 INTEGRATOR VBIAS BPF ±1 INTEGRATOR VBIAS BPF ±1 INTEGRATOR B A SLOT SELECT AFE CONFIGURATION Figure 1. Typical Functional Block Diagram |
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