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ADPD103 Datasheet(PDF) 44 Page - Analog Devices

Part # ADPD103
Description  TEMPERATURE AND POWER SPECIFICATIONS
PDF  53 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADPD103 Datasheet(HTML) 44 Page - Analog Devices

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Data Sheet
ADPD103
Rev. B | Page 43 of 52
Address
Data
Bit
Default
Value
Access Name
Description
0x43
[15:0]
0xADA5
R/W
SLOTA_AFE_CFG
AFE connection in Time Slot A.
0xADA5: analog full path mode (TIA_BPF_INT_ADC).
0xB065: TIA_ADC mode.
0xAE65: digital integration mode.
Others: reserved.
0x55
[15:13]
0x0
R/W
DIGINT_POWER
Power-down for Channel 2, Channel 3, and Channel 4 in
digital integration mode.
0: keep all channels powered up.
7: powers down Channel 2, Channel 3, and Channel 4.
12
0x0
R/W
Reserved
Write 0x0.
[11:10]
0x0
R/W
SLOTB_TIA_GAIN_4
TIAgain for Time Slot B, Channel 4 (PD4).
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
[9:8]
0x0
R/W
SLOTB_TIA_GAIN_3
TIAgain for Time Slot B, Channel 3 (PD3).
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
[7:6]
0x0
R/W
SLOTB_TIA_GAIN_2
TIAgain for Time Slot B, Channel 2 (PD2).
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
[5:4]
0x0
R/W
SLOTA_TIA_GAIN_4
TIAgain for Time Slot A, Channel 4 (PD4).
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
[3:2]
0x0
R/W
SLOTA_TIA_GAIN_3
TIAgain for Time Slot A, Channel 3 (PD3).
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
[1:0]
0x0
R/W
SLOTA_TIA_GAIN_2
TIAgain for Time Slot A, Channel 2 (PD2).
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.



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