ADPD103 datasheet(45/53 Pages) AD

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ADPD103

Data Sheet

Rev. B | Page 44 of 52

Address

Data

Bit

Default

Value

Access Name

Description

0x5A

[15:8]

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

DIG_INT_GAPMODE

Digital integration gapped mode enable.

0: no gap between negative and positive sample regions.

1: use SLOTA_AFE_FOFFSET for Time SlotA or SLOTB_AFE_

FOFFSET for Time Slot B to specify the gap in μs.

0x0

R/W

SLOTB_DIG_INT_SAMPLEMODE Digital integration single-sample pair mode for Time Slot B.

0: double sample pair mode.

1: single-sampled pair mode.

0x0

R/W

SLOTA_DIG_INT_SAMPLEMODE

Digital integration single-sample pair mode for Time Slot A.

0: double sample pair mode.

1: single-sampled pair mode.

[4:0]

0x0

R/W

Reserved

Write 0x0.

Table 23. AFE Configuration Registers, Time Slot B

Address

Data

Bit

DefaultValue

Access

Name

Description

0x3B

[15:11]

0x4

R/W

SLOTB_AFE_WIDTH

AFE integration window width (in 1 μs step) for Time Slot B.

[10:5]

0x17

R/W

SLOTB_AFE_OFFSET

AFE integration window coarse offset (in 1 μs step) for

Time Slot B.

[4:0]

0x1C

R/W

SLOTB_AFE_FOFFSET

AFE integration window fine offset (in 31.25 ns step) for

Time Slot B.

0x44

[15:8]

0x1C

R/W

SLOTB_AFE_MODE

0x1C: Time Slot B AFE setting for normal mode

(TIA_BPF_INT_ADC).

0x1D: Time Slot B AFE setting for digital integrate mode.

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

SLOTB_TIA_IND_EN

Enable Time Slot B TIA gain individual settings. When it is

enabled, the Channel 1 TIA gain is set via Register 0x44,

Bits[1:0], and the Channel 2 through Channel 4 TIA gain is

set via Register 0x55, Bits[11:6].

0: disable TIA gain individual setting.

1: enable TIA gain individual setting.

[5:2]

0xE

R/W

Reserved

Write 0xD.

[1:0]

0x0

R/W

SLOTB_TIA_GAIN

Transimpedance amplifier gain for Time Slot B. When

SLOTB_TIA_IND_EN is enabled, this value is for Time Slot B,

Channel 1 TIA gain. When SLOTB_TIA_IND_EN is disabled,

it is for all four Time Slot B channel TIA gain settings.

0: 200 kΩ.

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

0x45

[15:0]

0xADA5

R/W

SLOTB_AFE_CFG

AFE connection in Time Slot B.

0xADA5: analog full path mode (TIA_BPF_INT_ADC).

0xB065: TIA_ADC mode.

0xAE65: digital integration mode.

Others: reserved.

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