ADPD103 datasheet(50/53 Pages) AD

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Data Sheet

ADPD103

Rev. B | Page 49 of 52

Address

Data

Bit

Default Access Name

Description

0x4F

[15:7]

0x41

R/W

Reserved

Write 0x41.

0x0

R/W

PDSO_OE

PDSO pin output enable.

0x0

R/W

PDSO_IE

PDSO pin input enable.

0x1

R/W

Reserved

Write 0x1.

[3:2]

0x0

R/W

EXT_SYNC_SEL

Sample sync select.

00: use the internal 32 kHz clock with FSAMPLE to select sample timings.

01: use the INT pin to trigger sample cycle.

10: use the PDSO pin to trigger sample cycle.

11: reserved.

0x0

R/W

INT_IE

INT pin input enable.

0x0

R/W

Reserved

Write 0x0.

0x50

[15:7]

0x000

R/W

Reserved

Write 0x000.

0x0

R/W

PDSO_CTRL

Controls the PDSO output when the PDSO output is enabled (PDSO_OE =

0x1).

0x0: PDSO output driven low.

0x1: PDSO output driven by the AFE power-down signal.

0x0

R/W

CLK32M_CAL_EN

As part of the 32 MHz clock calibration routine, write 1 to begin the clock

ratio calculation. Read the result of this calculation from the CLK_RATIO

bits in Register 0x0A.

Reset this bit to 0 prior to reinitiating the calculation.

[4:0]

0x0

R/W

Reserved

Write 0x0.

0x5F

[15:3]

0x0000

R/W

Reserved

Write 0x0000.

0x0

R/W

SLOTB_DATA_HOLD

Setting this bit prevents the update of the data registers corresponding to

Time Slot B. Set this bit to ensure that unread data registers are not updated,

guaranteeing a contiguous set of data from all four photodiode channels.

1: hold data registers for Time Slot B.

0: allow data register update.

0x0

R/W

SLOTA_DATA_HOLD

Setting this bit prevents the update of the data registers corresponding to

Time SlotA. Set this bit to ensure that unread data registers are not updated,

guaranteeing a contiguous set of data from all four photodiode channels.

1: hold data registers for Time Slot A.

0: allow data register update.

0x0

R/W

FIFO_ACCESS_ENA

Set to 1 twice to enable FIFO access. It is necessary to write 1 to the

FIFO_ACCESS_ENA bit in two consecutive write operations in order to

read data from the FIFO. During clock calibration, set to 1 to force the

32 MHz clock to run. For power savings, reset to 0 when the previously

described operations are complete.

Clock speed setting is only relevant during digital integrate mode.

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