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Data Sheet

ADPD103

Rev. B | Page 25 of 52

written to the FIFO. Note that both time slots can be enabled to

use the FIFO, but only if their output data rate is the same.

Output data rate = fSAMPLE/N

where:

fSAMPLE is the sampling frequency.

N is the averaging factor for each time slot (NA for Time Slot A

and NB for Time Slot B). In other words, NA = NB must be true

to store data from both time slots in the FIFO.

Data packets are written to the FIFO at the output data rate. A

data packet for the FIFO consists of a complete sample for each

enabled time slot. Data for each photodiode channel can be stored

as either 16 or 32 bits. Each time slot can store 2, 4, 8, or 16

bytes of data per sample, depending on the mode and data

format. To ensure that data packets are intact, new data is only

written to the FIFO if there is sufficient space for a complete

packet. Any new data that arrives when there is not enough

space is lost. The FIFO continues to store data when sufficient

space exists. Always read FIFO data in complete packets to

ensure that data packets remain intact.

The number of bytes currently stored in the FIFO is available in

available and automatically generates when a specified amount

of data is written to the FIFO.

Interrupt-Based Method

To read data from the FIFO using an interrupt-based method,

use the following procedure:

1. In program mode, set the configuration of the time slots as

desired for operation.

2. Write Register 0x11 with the desired data format for each

time slot.

3. Set FIFO_THRESH in Register 0x06, Bits[13:8] to the

interrupt threshold. A good value for this is the number of

16-bit words in a data packet, minus 1. This causes an

interrupt to generate when there is at least one complete

packet in the FIFO.

4. Enable the FIFO interrupt by writing a 0 to the FIFO_

INT_MASK in Register 0x01, Bit 8. Also, configure the

interrupt pin (INT) by writing the appropriate value to the

bits in Register 0x02.

5. Enter normal operation mode by setting Register 0x10 to

0x2.

6. When an interrupt occurs

a. There is no requirement to read the FIFO_SAMPLES

is one or more full packets. Optionally, the interrupt

routine can check for the presence of more than one

available packet by reading this register.

b. Write 1 to the FIFO_ACCESS_ENA bit (Register 0x5F,

Bit 0) twice in two consecutive write operations.

c. Read a complete packet using one or more multiword

accesses using Register 0x60. Reading the FIFO

automatically frees the space for new samples.

d. Write 0 to the FIFO_ACCESS_ENAbit (Register 0x5F,

Bit 0).

The interrupt automatically clears when enough data is read

from the FIFO to bring the data level below the threshold.

Polling Method

To read data from the FIFO in a polling method, use the

following procedure:

1. In program mode, set the configuration of the time slots as

desired for operation.

2. Write Register 0x11 with the desired data format for each

time slot.

3. Enter normal operation mode by setting Register 0x10 to 2.

Next, begin the polling operations.

1. Wait for the polling interval to expire.

2. Read the FIFO_SAMPLES bits (Register 0x00, Bits[15:8]).

3. If FIFO_SAMPLES ≥ the packet size, read a packet using

the following steps:

a. Write 1 to the FIFO_ACCESS_ENA bit (Register 0x5F,

Bit 0) twice in two consecutive write operations.

b. Read a complete packet using one or more multiword

accesses using Register 0x60. Reading the FIFO

automatically frees the space for new samples.

c. Write 0 to the FIFO_ACCESS_ENA bit (Register 0x5F,

Bit 0).

d. Repeat Step 1.

When a mode change is required, or any other disruption to

normal sampling is necessary, the FIFO must be cleared. Use

the following procedure to clear the state and empty the FIFO:

1. Enter program mode by setting Register 0x10 to 0x1.

2. Write 1 to the FIFO_ACCESS_ENA bit (Register 0x5F,

Bit 0) twice in two consecutive write operations.

3. Write 1 to Register 0x00, Bit 15.

4. Write 0 to the FIFO_ACCESS_ENAbit (Register 0x5F, Bit 0).

Reading Data from Registers Using Interrupts

The latest sample data is always available in the data registers and is

updated simultaneously at the end of each time slot. The data value

for each photodiode channel is available as a 16-bit value in Regis-

ter 0x64 through Register 0x67 for Time SlotA, and Register 0x68

through Register 0x6B for Time Slot B. If allowed to reach their

maximum value, Register 0x64 through Register 0x6B clip. If

to 27 bits) values for each channel are available in Register 0x70

through Register 0x77 for Time Slot A and Register 0x78 through

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