PI3749 datasheet(18/26 Pages) VICOR

18 / 26 page

Cool-Power® ZVS Switching Regulators

Rev 1.6

vicorpower.com

Page 18 of 26

09/2016

800 927.9474

PI3749-x0

number of ceramic capacitors used to calculate the individual

capacitor’s RMS current. Table 2 includes the recommended

input and output ceramic capacitor. It is very important to verify

that the voltage supply source as well as the interconnecting line

are stable and do not oscillate.

Input Filter case 1; Inductive source and local, external, input

decoupling capacitance with negligible ESR (i.e.: ceramic type)

The voltage source impedance can be modeled as a series Rline

Lline circuit. The high performance ceramic decoupling capacitors

will not significantly damp the network because of their low ESR;

therefore in order to guarantee stability the following conditions

must be verified:

Where, rEQ_IN can be calculated by dividing the lowest line

voltage by the full load input current. It is critical that the

line source impedance be at least an octave lower than the

converter’s dynamic input resistance, Equation (4). However,

Rline cannot be made arbitrarily low otherwise Equation (3)

is violated and the system will show instability, due to under-

damped RLC input network.

Input Filter case 2; Inductive source and local, external input

decoupling capacitance with significant RCIN_EXT ESR

(i.e.: electrolytic type)

In order to simplify the analysis in this case, the voltage source

impedance can be modeled as a simple inductor Lline. Notice

that, the high performance ceramic capacitors CIN_INT within

the PI3749-x0 should be included in the external electrolytic

capacitance value for this purpose. The stability criteria will be:

Equation (6) shows that if the aggregate ESR is too small – for

example by using very high quality input capacitors (CIN_EXT)

– the system will be under-damped and may even become

destabilized. Again, an octave of design margin in satisfying

Equation (5) should be considered the minimum.

Note: When applying an electrolytic capacitor for input filter

damping the ESR value must be chosen to avoid loss of converter

efficiency and excessive power dissipation in the

electrolytic capacitor.

Parallel Operation

PI3749-x0 can be connected in parallel up to two phases, with

interleaving. Parallel interleaved modules can be used to increase

the output current capability of a single power rail and reduce

output voltage ripple. Figure 27 shows the proper connection

of two regulators in parallel interleaved operation. Connecting

a higher number of modules (up to six maximum) is possible

without interleaving or synchronization. Connecting groups

of interleaved modules would be the best configuration for

applications requiring higher current than two modules can

produce. The user must consider a worst case sharing error of

+/-10% when considering a two unit parallel system to avoid

overloading one module or tripping current limit during

load transients.

By connecting the EAO pins and SGND pins of each module

together, the regulators will share the output current equally,

provided each power inductor is the same value and the output

ripple is not excessive. Connecting all TRK pins will force all units

to track each other during soft-start. Additionally, all units EN

pins must be released to allow the units to start (See Figure 27).

To provide synchronization between regulators over the entire

operational frequency range, the Power Good (PGD) pin must

be connected to the lead regulator’s (#1) SYNCI pin and a 2.5kΩ

Resistor, R1, must be placed between SYNCO (#2) return and

the lead regulator’s SYNCI (#1) pin, as shown in Figure 27. In

this configuration, at system soft-start, the PGD pin pulls SYNCI

low forcing the lead regulator to initialize the open-loop startup

synchronization. Once the regulators reach regulation, SYNCI

is released and the system is now synchronized in a closed-

loop configuration which allows the system to maintain correct

synchronization when any of the individual regulators begin to

enter variable frequency mode.

Any fault event flagged by one regulator will disable the other

regulators. The regulators will not be synchronized during a fault

or during startup (resulting in higher output ripple for that period

of time) until the PGD pin is released.

line >

line

IN_INT + CIN_EXT

• r

EQ_IN

(3)

(

)

line << rEQ_IN

(4)

EQ_IN > RCIN_EXT

(5)

line

IN_INT • RCIN_EXT

(6)

< r

EQ_IN

SGND

Vin

Vout

PGND

EAIN

TRK

EAO

PI3749-x0

(#1)

Cin

Cout

SGND

Vin

Vout

PGND

EAIN

PI3749-x0

(#2)

Cout

EAO(#2)

TRK(#2)

EN(#2)

Vin

Cin

PGD

SYNCI

SYNCO

SYNCI (#2)

SYNCO (#2)

TRK

EAO

EAO(#1)

TRK (#1)

EN (#1)

PGD

SYNCI

SYNCO

SYNCI(#1)

SYNCO(#1)

VS1

VS2

VS1

VS2

Figure 27 — PI3749-x0 parallel operation

PI3749 Datasheet(PDF) 18 Page - Vicor Corporation

PI3749 Datasheet(HTML) 18 Page - Vicor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL