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PI3749 Datasheet(PDF) 20 Page - Vicor Corporation |
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PI3749 Datasheet(HTML) 20 Page - Vicor Corporation |
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20 / 26 page ![]() Cool-Power® ZVS Switching Regulators Rev 1.6 vicorpower.com Page 20 of 26 09/2016 800 927.9474 PI3749-x0 Figure 28 — Data transfer on the I2C bus I2C Addressing The PI3749-20 is hardware compatible with the NXP I2C Bus Specification Version 2.1, January 2000, in Standard Mode (100kHz) for all bus timing and voltage levels up to 5.5V. It operates as a slave on the I2C bus. The PI3749-20 I2C interface responds to the address programmed by the two I2C Address pins, ADR1 and ADR0. The address pins are three level inputs, providing nine possible combination pairs, although only eight of these combinations are unique, as shown in table 3. Considering only the 7 bit address sub-field, the high-order address bits <6> through <4> are hardcoded to 4’b1001, while the lower order address bits <3> through <0> are modified by the ADRx pins. Note that the state of the ADRx pins is resolved on each I2C address transfer. Therefore the PI3749-20 address can be changed while the regulator is powered up and in operation. I2C Command Structure Depending on the state of the read/write bit, two types of transfers are possible: a. Write: Data transferred from the I2C master to the PI3749-20 slave The first byte is transmitted by the master and includes the slave address and the R/W bit set to write (as shown in the last column of table 3.) The second byte is also transmitted by the master and is the write data. The slave responds between each byte with an acknowledge bit. b. Read: Data returned from the PI3749-20 slave to the master The first byte is transmitted by the master and includes the slave address but the R/W bit is set to read. The slave responds to the first byte (the address transmitted by the master) with an acknowledge bit. The second byte is transmitted by the slave back to the master and is the read data. The master responds after the read data byte with a not-acknowledge bit (since the PI3749-20 read data are all single byte registers). Per the I2C standard, the master generates all serial clock pulses, and all data is transferred MSB first. ADDRx state Resultant I2C address sub-field Sub-field bit positions <7.1> Fully formed address write word (including lsb of the transfer set for a write) ADR1 ADR0 Hexadecimal Decimal Binary Binary L L 7’h48 72 7’b100_1000 8’b1001_0001 L M 7’h49 73 7’b100_1001 8’b1001_0011 L H 7’h4A 74 7’b100_1010 8’b1001_0101 M L 7’h4B 75 7’b100_1011 8’b1001_0111 M M 7’h4C 76 7’b100_1100 8’b1001_1001 M H 7’h4D 77 7’b100_1101 8’b1001_1011 H L 7’h4E 78 7’b100_1110 8’b1001_1101 H M 7’h4F 79 7’b100_1111 8’b1001_1111 H H 7’h4F 79 7’b100_1111 8’b1001_1111 Table 3 — I2C Address selection |
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