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XMC4100 Datasheet(PDF) 72 Page - Infineon Technologies AG |
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XMC4100 Datasheet(HTML) 72 Page - Infineon Technologies AG |
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72 / 94 page ![]() XMC4100 / XMC4200 XMC4000 Family Electrical Parameters Data Sheet 72 V1.3, 2015-10 Positive Load Step Examples System assumptions: f CPU = fSYS, target frequency fCPU = 80 MHz, main PLL fVCO = 480 MHz, stepping done by K2 divider, t PLSS between individual steps: 24 MHz - 48 MHz - 80 MHz (K2 steps 20 - 10 - 6) 24 MHz - 60 MHz - 80 MHz (K2 steps 20 - 8 - 6) Table 42 Power Sequencing Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Positive Load Step Current ΔI PLS SR - − 50 mA Load increase on V DDP Δt ≤ 10 ns Negative Load Step Current ΔI NLS SR - − 150 mA Load decrease on V DDP Δt ≤ 10 ns V DDC Voltage Over- / Undershoot from Load Step ΔV LS CC - − ±100 mV For maximum positive or negative load step Positive Load Step Settling Time t PLSS SR 50 − - μs Negative Load Step Settling Time t NLSS SR 100 − - μs External Buffer Capacitor on V DDC C EXT SR 3 4.7 6 μF In addition C = 100 nF capacitor on each V DDC pin Subject to Agreement on the Use of Product Information |
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