XMC4100 datasheet(76/94 Pages) INFINEON

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XMC4100 / XMC4200

XMC4000 Family

Electrical Parameters

Data Sheet

V1.3, 2015-10

3.3.6

JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug

interface. The JTAG module is fully compliant with IEEE1149.1-2000.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Note: Operating conditions apply.

Table 46

JTAG Interface Timing Parameters

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

TCK clock period

–

For C

L =20pF

on TDO

TCK clock period

–

For C

L =50pF

on TDO

TCK high time

–

TCK low time

–

TCK clock rise time

––4ns

TCK clock fall time

––4ns

TDI/TMS setup

to TCK rising edge

6––ns

TDI/TMS hold

after TCK rising edge

6––ns

TDO valid after TCK falling

edge

1) (propagation delay)

1) The falling edge on TCK is used to generate the TDO timing.

––17

L =50pF

3––ns

L =20pF

TDO hold after TCK falling

edge

2––ns

TDO high imped. to valid

from TCK falling edge

1)2)

2) The setup time for TDO is given implicitly by the TCK cycle time.

––14

L =50pF

TDO valid to high imped.

from TCK falling edge

–

13.5

L =50pF

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