MTL005 datasheet(6/50 Pages) ETC

6 / 50 page

MYSON

TECHNOLOGY

MTL005

Rev 0.9

Revision 0.9

- 6 -

2000/12/29

3. FUNCTIONAL DESCRIPTION

3.1 Input Processor

General Description

The function of Input Interface is to provide the interface between MTL005 and external input devices. It can

process both non-interlaced and interlaced RGB graphic input, YUV video input, and digital RGB input

compliant with digital LVDS/PanelLink TMDS interface. It also contains the built-in YUV to RGB color space

converter.

3.1.1

RGB Input Format

Since MTL005 is a low cost solution, the RGB input port can only work in Single Pixel mode (24 bits). The

R/G/BIN ports are sampled at the rising edge of the RGB input clock.

3.1.2

TMDS Input Format

The Digital RGB input port works likewise as described in Sec 3.1.1 except one more input pin is needed:

Digital Input Enable DIEN.

With a single pixel input interface, the supported format is up to true color, including 18 bit/pixel or 24 bit/pixel.

3.1.3

YUV Input Format

The YUV input port supports interlaced video data from the most common video decoder ICs like SAA711x.

The 16 bit data bus is shared with the ports RIN[7:0] and GIN[7:0]. The 16 bit data is sampled at the rising

edge of the shared video clock VPCLK when the shared data enable HREF is active. The supported formats

are YUV4:1:1 and YUV4:2:2 with CCIR601/CCIR656 standard.

3.1.4

Input HSYNC Path

Besides the pin HSYNC, MTL005 provides another pin RAWHS to support Sync Processor in MTL005.

Generally, the HSYNC generated by an ADC may have a very narrow pulse width and a different polarity

from the original HSYNC provided by the source. The RAWHS input provides the path of original HSYNC

connection to MTL005, which makes Sync Processor in MTL005 work correctly.

3.1.5

YUV to RGB Converter

It is used to convert YCbCr format into RGB format. The basic equations are as follows:

R = Y + 1.371(Cr - 128)

G = Y - 0.698(Cr - 128) - 0.336(Cb - 128)

B = Y + 1.732(Cb - 128)

3.1.6

De-interlace mode

For interlace input, MTL005 features several de-interlacing algorithms for processing interlaced video data

depending on the type of input images.

Toggle Mode

In this mode, only one field is displayed at the time. First field and second field is toggled displayed. The

missing lines are calculated from duplicating the neighbor lines.

Spatial Mode

In this mode, two fields are toggled displayed, just like Toggle mode. The missing lines are calculated from

interpolating the neighbor lines. An average good quality for still and moving pictures is achieved in this mode.

3.1.7

Sync Processor

The V/H SYNC processing block performs the functions of Composite signal separation/insertion, SYNC

inputs presence check, frequency counting, polarity detection and control. It contains a de-glitch circuit to

filter out any pulse shorter than one OSC period treated as noises on V/H SYNC pulses.

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