MTL005 datasheet(10/50 Pages) ETC

10 / 50 page

MYSON

TECHNOLOGY

MTL005

Rev 0.9

Revision 0.9

- 10 -

2000/12/29

3.3 Output Processor

General Description

Output processor provides the interface for both LCD panel and OSD controller. output frame rate must be

equal to input frame rate and output display time must be equal to input display time, because of no frame

buffer.

3.3.1

Display Timing Generation

Output frame rate is equal to input frame and external frame buffer is not needed.

Fig. 3.3.1 Display Timing modes

3.3.2

OSD Overlay

MTL005 allows the integration of overlay data with the scaled output pixel stream. It provides a fully

compatible OSD interface. Individual OSD clock, OSD HSYNC and OSD VSYNC are sent to external OSD

device. MTL005 receives OSD Enable, OSD Red, OSD Green, and OSD Blue from external OSD device.

3.3.3

RGB Output Format

MTL005 output interface consists of two pixel ports, each containing Red, Green, and Blue color information

with a resolution of 6/8 bits per color. These two ports are mapped to PORT1 and PORT2.

The control signals for output port are display horizontal sync signal (DHSYNC), display vertical sync signal

(DVSYNC) and display data enable signal (DDEN).

All the signals mentioned above are synchronous to the output clock. The output timing relative to the active

edge of the output clock is programmable.

There are two RGB output formats:

Single Pixel Mode

It is designed to support TFT panels with single pixel input. Only PORT1 is active. The frequency of DCLK1

is equal to internal display clock.

Dual Pixel Mode

It is designed to support TFT panels with dual pixel input. PORT1 and PORT2 are used. The first pixel is at

PORT1, and the second at PORT2.

X: lock position

Input Frame

Output

Frame

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