TH6503 datasheet(4/24 Pages) ETC

4 / 24 page

TH6503 USB Low-Speed Interface

Figure 4. Serial Data IN

Data OUT Transfer

(from the TH6503 to the microcontroller)

An impulse on the SDI link at SIN = 0 represents

the OUT packet sync for an OUT transfer. With the

falling SCK edge the data (LSB first) is shifted to

SDO and with rising SCK edge accepted by the

microcontroller. The StatusRegister is transferred

initially followed by the CntOutRegister and finally

the OUT FIFO data. If the transfer is terminated after

less than 8 clock pulses, only single StatusRegister

bits are read. Linear transfer is interrupted by SIN

= 1 and must be initiated with a new OUT packet

sync at SIN = 0. Two impulses on the SDI link

initiate a transfer of the CntOutRegisters and of the

following

OUT

FIFO

bytes

without

the

StatusRegister. A zero data transfer is identified by

an OUT Count Byte value of 0. The end of a Data

OUT transfer clears the SET bit in the

CntOutRegister

and

the

bit

the

StatusRegister to make the next USB OUT or

Setup transfer possible.

Figure 5. OUT Transfer of StatusRegister

Microcontroller

Interface

(continued)

SCK

SIN

SDO

SDI

Status0

Status1

Status2

Status n

/INT

Microcontroller

latches Data

on rising edge

of SCK

Bridge shifts

Data on falling

edge of SCK

End of

Transfer

Clear Interrupt Latch

SDI pulse with SIN=0:

- copy StatusRegister to Shift Register for Serial Data Out

any break

after identify the

/INT source possible

n <= 7

SCK

SIN

SDO

SDI

n+8

/INT

Bridge latches

Data on rising

edge of SCK

Microcontroller shifts

Data on falling

edge of SCK

End of IN Transfer

Microcontroller outputs

Adr/CntInRegister Bit 0 / AC0

on SDI

AC7

Data Bit 0

Bit n

AC0

AC1

AC2

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