TH6503 datasheet(5/24 Pages) ETC

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TH6503 USB Low-Speed Interface

Figure 6. Complete Data OUT Transfer

Figure 7. OUT Transfer, only CntOutRegister and OUT FIFO Bytes

Interrupt Function

If SIN = 1, the SDO pin can be used to generate an

interrupt signal. The interrupt is low active. It is

triggered if a control transfer is made from the USB

host or a control or interrupt transfer is made to the

USB host and one of the ID12, ID0 or OD bits has

been set in the StatusRegister <3-1> or at high

level of the WAKE pin. An interrupt signal is also

triggered on RESUME and USB_RESET.

The interrupt latch is reset on reading the status

ing StatusRegister, this interrupt is latched and

the interrupt source is after new StatusRegister

reading visible.

A WAKE interrupt is only generated during the stop

state (bits SO and/or SMC in the BridgeConfig

Microcontroller

Interface

(continued)

SCK

SIN

SDO

SDI

n+16

Status0

Status1

Status2

Status7

CNT0

CNT7

FIFO Bit 0

Bit n

/INT

Microcontroller

latches Data

on rising edge

of SCK

Bridge shifts

Data on falling

edge of SCK

End of OUT Transfer

(OUT Tranfer after reading

the Status -and CntOutRegister

with SIN=0 clears

EP0 Out Done

Bridge outputs

next Register (CntOutRegister)

Bit 0 on SDO

Clear Interrupt Latch

SDI pulse with SIN=0:

- transfer StatusRegister to Serial Data Out

SCK

SIN

SDO

SDI

n+8

Microcontroller

latches Data

on rising edge

of SCK

Bridge shifts

Data on falling

edge of SCK

End of OUT Transfer

(OUT Tranfer > 8 clocks

the Status -and CntOutRegister

with SIN=0 clears

EP0 Out Done

Bridge outputs

next Register (FIFO)

Bit 0 on SDO

Two SDI pulses with SIN=0:

- transfer CntOutRegister and OUT FIFO Bytes

to Serial Data Out

CNT0

CNT1

CNT7

FIFO Bit 0

Bit n

/INT

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