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PCM1803DBR Datasheet(PDF) 4 Page - Texas Instruments |
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PCM1803DBR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 20 page ![]() www.ti.com RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS PCM1803 SLES125 – NOVEMBER 2004 over operating free-air temperature range MIN NOM MAX UNIT Analog supply voltage, VCC 4.5 5 5.5 V Digital supply voltage, VDD 2.7 3.3 3.6 V Analog input voltage, full-scale (–0 dB) 3 Vp-p Digital input logic family TTL System clock 8.192 49.152 MHz Digital input clock frequency Sampling clock 32 96 kHz Digital output load capacitance 10 pF Operating free-air temperature, TA –25 85 °C All specifications at T A = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 24 Bits DATA FORMAT Audio data interface format Left-justified, I2S, right-justified Audio data bit length 20, 24 Bits Audio data format MSB-first, 2s complement fS Sampling frequency 16 44.1 96 kHz 256 fS 4.096 11.2896 24.576 384 fS 6.144 16.9344 36.864 System clock frequency MHz 512 fS 8.192 22.5792 49.152 768 fS 12.288 33.8688 – INPUT LOGIC VIH(1) 2 VDD VIL(1) 0 0.8 Input logic-level voltage VDC VIH(2)(3) 2 5.5 VIL(2)(3) 0 0.8 IIH(1)(2) VIN = VDD ±10 IIL(1)(2) VIN = 0 ±10 Input logic-level current µA IIH(3) VIN = VDD 65 100 IIL(3) VIN = 0 ±10 OUTPUT LOGIC VOH(4) IOUT = –4 mA 2.8 Output logic-level voltage VDC VOL(4) IOUT = 4 mA 0.5 DC ACCURACY Gain mismatch, channel-to-channel ±1 ±3 % of FSR Gain error ±2 ±4 % of FSR Bipolar zero error HPF bypass ±0.4 % of FSR (1) Pins 10–11: LRCK, BCK (Schmitt-trigger input, in slave mode) (2) Pin 15: SCKI (Schmitt-trigger input, 5-V tolerant) (3) Pins 7–9, 16–20: PDWN, BYPAS, TEST, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-k Ω typical pulldown resistor, 5-V tolerant) (4) Pins 10–12: LRCK, BCK (in master mode), DOUT 4 |
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