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BCK

LRCK

DOUT

T0018-02

SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM

PCM1803

SLES125 – NOVEMBER 2004

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

BCK period

150

1000

ns

BCK pulse duration, HIGH

65

600

ns

BCK pulse duration, LOW

65

600

ns

Delay time, BCK falling edge to LRCK valid

–10

20

ns

LRCK period

10

65

µs

Delay time, BCK falling edge to DOUT valid

–10

20

ns

Delay time, LRCK edge to DOUT valid

–10

20

ns

Rising time of all signals

20

ns

Falling time of all signals

20

ns

measured from 10% to 90% of IN/OUT signal swing. Load capacitance of all signals

is 20 pF.

Figure 21. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as

Outputs)

In slave mode, the PCM1803 operates under LRCK, synchronized with system clock SCKI. The PCM1803 does

not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK

and SCKI.

If the relationship between LRCK and SCKI changes more than

±6 BCKs for 64 BCK/frame (±5 BCKs for 48

and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI occurs.

In case of changes less than

±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization does

not occur and the previously explained digital output control and discontinuity do not occur.

Figure 22 illustrates the digital output response for loss of synchronization and resynchronization. During

undefined data, the PCM1803 can generate some noise in the audio signal. Also, the transition of normal to

undefined data and undefined or zero data to normal creates a discontinuity in the data of the digital output,

which can generate some noise in the audio signal.

It is recommended to set PDWN (pin 7) to LOW once to get stable analog performance when the sampling rate,

interface mode, data format, or oversampling control is changed.

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