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NORMAL DATA

ZERO DATA

UNDEFINED

DATA

NORMAL DATA

SYNCHRONOUS

ASYNCHRONOUS

SYNCHRONOUS

Resynchronization

Synchronization Lost

DOUT

State of Synchronization

T0020-05

POWER DOWN

HPF BYPASS

OVERSAMPLING RATIO CONTROL

PCM1803

SLES125 – NOVEMBER 2004

Figure 22. ADC Digital Output for Loss of Synchronization and Resynchronization

PDWN (pin 7) controls operation of the entire ADC. During power-down mode, supply current for the analog

portion is shut down and the digital portion is reset; also, DOUT (pin 12) is disabled. It is acceptable to halt the

system clock during power-down mode so that power dissipation is minimized. The minimum LOW pulse

duration of PDWN pin is 100 ns.

Table 4. Power-Down Control

PWDN

Power-Down Mode

LOW

Power-down mode

HIGH

Normal operation mode

The built-in function for dc-component rejection can be bypassed by BYPAS (pin 8) control. In bypass mode, the

dc component of the input analog signal, internal dc offset, etc., also are converted and included in the digital

output data.

Table 5. HPF Bypass Control

BYPAS

HPF (High-Pass Filter) Mode

LOW

Normal (no dc component in DOUT) mode

HIGH

Bypass (dc component in DOUT) mode

OSR (pin 16) controls oversampling ratio of the delta-sigma modulator,

×64 or ×128. The ×128 mode is available

Table 6. Oversampling Control

OSR

Oversampling Ratio

LOW

×64

HIGH

×128 (f

16