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INTERFACE TIMING

BCK

LRCK

DOUT

1.4 V

1.4 V

T0017-02

PCM1803

SLES125 – NOVEMBER 2004

Figure 20 and Figure 21 illustrate the interface timing in slave mode and master mode, respectively.

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

BCK period

ns

BCK pulse duration, HIGH

1.5

× t

(SCKI)

ns

BCK pulse duration, LOW

1.5

× t

(SCKI)

ns

LRCK setup time to BCK rising edge

40

ns

LRCK hold time to BCK rising edge

20

ns

LRCK period

10

µs

Delay time, BCK falling edge to DOUT valid

–10

40

ns

Delay time, LRCK edge to DOUT valid

–10

40

ns

Rising time of all signals

20

ns

Falling time of all signals

20

ns

measured from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT is

Figure 20. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as

Inputs)

14