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System Clock

2.6 V

2.2 V

1.8 V

Internal Reset

DOUT

Zero Data

Normal Data

Reset

Reset Removal

1024 System Clocks

T0014-05

SERIAL AUDIO DATA INTERFACE

INTERFACE MODE

DATA FORMAT

PCM1803

SLES125 – NOVEMBER 2004

Figure 18. Internal Power-On Reset Timing

The PCM1803 interfaces the audio system through BCK (pin 11), LRCK (pin 10), and DOUT (pin 12).

The PCM1803 supports master mode and slave mode as interface modes, and they are selected by MODE1 (pin

20) and MODE0 (pin 19) as shown in Table 2.

In master mode, the PCM1803 provides the timing of serial audio data communications between the PCM1803

and the digital audio processor or external circuit. While in slave mode, the PCM1803 receives the timing for data

transfers from an external controller.

Table 2. Interface Mode

MODE1

MODE0

INTERFACE MODE

0

0

0

1

1

0

1

1

Master Mode

In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated

in the clock circuit of the PCM1803. The frequency of BCK is fixed at LRCK

× 64. The 768-f

available in master mode.

Slave Mode

In slave mode, BCK and LRCK work as input pins. The PCM1803 accepts the 64-BCK/LRCK or 48-BCK/LRCK

The PCM1803 supports four audio data formats in both master and slave modes, and the data formats are

selected by FMT1 (pin 18) and FMT0 (pin 17) as shown in Table 3. Figure 19 illustrates the data formats in slave

and master modes.

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