PCM1803DBR datasheet(11/20 Pages) TI

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DEVICE INFORMATION

SYSTEM CLOCK

SCKI

0.8 V

SCKI

2.0 V

t(SCKL)

t(SCKH)

T0005-07

POWER-ON RESET SEQUENCE

PCM1803

SLES125 – NOVEMBER 2004

The PCM1803 supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling

frequency. The system clock must be supplied on SCKI (pin 15).

The PCM1803 has a system clock-detection circuit that automatically senses if the system clock is operating at

256 fS, 384 fS, 512 fS, or 768 fS in slave mode. In master mode, the system clock frequency must be selected by

MODE0 (pin 19) and MODE1 (pin 20), and 768 fS is not available. The system clock is divided automatically into

128 fS and 64 fS, and these frequencies are used to operate the digital filter and the delta-sigma modulator.

Table 1 shows the relationship of typical sampling frequency and system clock frequency, and Figure 17 shows

system clock timing.

Table 1. Sampling Frequency and System Clock Frequency

SAMPLING FREQUENCY (kHz)

SYSTEM CLOCK FREQUENCY (MHz)

256 fS

384 fS

512 fS

768 fS(1)

8.1920

12.2880

16.3840

24.5760

44.1

11.2896

16.9344

22.5792

33.8688

12.2880

18.4320

24.5760

36.8640

16.3840

24.5760

32.7680

49.1520

88.2

22.5792

33.8688

45.1584

–

24.5760

36.8640

49.1520

–

(1)

Slave mode only.

SYMBOL

PARAMETER

MIN

MAX

UNIT

t(SCKH)

System clock pulse duration, HIGH

t(SCKL)

System clock pulse duration, LOW

Figure 17. System Clock Timing

The PCM1803 has an internal power-on reset circuit, and initialization (reset) is performed automatically at the

time when power-supply voltage (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical) and for 1024 system

clock cycles after VDD > 2.2 V (typical), the PCM1803 stays in the reset state and the digital output is forced to

zero. The digital output becomes valid when a time period of 4480/fS has elapsed following release from the

reset state. Figure 18 illustrates the internal power-on reset timing and the digital output for power-on reset.

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