Philips Semiconductors

Product data

PCA9501

2-kbit EEPROM and 6 address pins

2003 Sep 12

5

FUNCTIONAL DESCRIPTION

SW00788

WRITE PULSE

DATA FROM

SHIFT REGISTER

POWER-ON

RESET

READ PULSE

DATA TO

SHIFT REGISTER

I/O0 TO I/O7

100

µA

S

DQ

FF

S

DQ

FF

TO INTERRUPT LOGIC

Figure 4. Simplified schematic diagram of each I/O

DEVICE ADDRESSING

Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9501 is shown in

Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.

0

A5

A4

A3

A2

A1

A0

A5

1A4

A3

A2

A1

A0

a.

b.

(a) I/O EXPANDER

(b) MEMORY

SW02006

SLAVE ADDRESS

SLAVE ADDRESS

HARDWARE

PROGRAMMABLE

FIXED

FIXED

R/W

R/W

HARDWARE

PROGRAMMABLE

Figure 5. PCA9501 slave addresses

The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write

operation.

CONTROL REGISTER

after a successful acknowledgment of the slave address.

It contains the I/O operation information.