MLX71122_16 datasheet(42/59 Pages) MELEXIS

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MLX71122

300 to 930MHz FSK/FM/ASK Receiver

Datasheet

REVISION 014 – AUGUST, 2016

Page 42 of 59

390 10 71122 01

4.1.2. Control Word R1

Name

Bits

Description

CPCUR

[1:0]

charge pump current setting

100µA

400µA

400µA static down

400µA static up

#default

PFDPOL

[2]

PFD output polarity

negative

positive

#default

LDERR

[3]

lock detector time error

15ns

30ns

#default

LDTIME

[5:4]

lock detection time

2/fR

4/fR

8/fR

16/fR

#default

minimum time span before lock in

fR is the reference oscillator frequency fRO divided by R, see section 4.1.5 (R4)

RSSIGAIN

[6]

sensitivity of RSSI voltage

low gain

high gain

(~39mV/dB)

(~51mV/dB)

#default

VCORANGE

[7]

VCO range

3V supply

5V supply

#default

VCO range setting for different VCCs.

VCOCUR

[8]

VCO core current

450µA

520µA

#default

VCOBUF

[9]

VCO buffer current

900µA

1040µA

#default

PRESCUR

[10]

prescaler 32/33 reference current

20µA

30µA

#default

30µA may be used for fRF = 868/915MHz

SHOWLD

[11]

function of LDRSSIL bit

RSSIL (RSSI low flag)

LD (lock detection flag)

#default

select output data of LDRSSIL, see section 4.1.8 (R7)

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