MLX71122_16 datasheet(18/59 Pages) MELEXIS

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MLX71122

300 to 930MHz FSK/FM/ASK Receiver

Datasheet

REVISION 014 – AUGUST, 2016

Page 18 of 59

390 10 71122 01

tot

PFD

LO1

















(6)

Since

LO 

,the channel frequency step, fCH, ,is not equal to the phase-frequency detector (PFD)

frequency fPFD.

For LO2 high-side injection, the channel step size fCH is given by

LO2

PFD

LO2









(7)

while the following equation is valid for LO2 low-side injection:

LO2

PFD

LO2









(8)

3.1.1. Calculation of Counter Settings

Frequency planning and the selection of the MLX71122’s PLL counter settings are straightforward and can

be laid out on the following procedure.

For this type of counter, it is necessary that

A 

For discrete frequency tuning without equal channel steps:

Find a combination of R, A and N to obtain VCO

from equations (1), (2), (3) or (4). A large value for R is not

always necessary to get high resolution tuning. A combination of

TOT

and R can almost always be found

which will give sufficient frequency accuracy even with a high PLL reference frequency. For example,

433.92MHz can be tuned with a 10MHz crystal with



and

979



TOT

with an 8.3kHz error.

For equal channel steps without gaps:

It is necessary that

N 

, it follows

)

(





, so



and

1024







tot

(9)

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