MLX71122_16 datasheet(31/59 Pages) MELEXIS

31 / 59 page

MLX71122

300 to 930MHz FSK/FM/ASK Receiver

Datasheet

REVISION 014 – AUGUST, 2016

Page 31 of 59

390 10 71122 01

The inputs are the RO frequency, output of the 2

nd mixer, two register words (IFFPRES and RIFF, see 4.1.6

and 4.1.7) and 2 register bits (IFFHLT and IFFTUNE, see 4.1.7). The tuning circuit is working when IFFTUNE is

HIGH and IFFHLT is LOW. If IFFHLT is HIGH then the digital tuning value IFFVAL remains at the last value. At

falling transitions of IFFTUNE the preset value IFFPRES is loaded into the internal IFFVAL register and the

tuning stops as well. IFFVAL and IFFSTATE (see 4.1.8) can be read out from register 7 if the MFO pin is

programmed as SPI output (see 4.1.4). IFFSTATE shows the last action of the tuning circuit. It can show if

the last value was increased, decreased or kept. A fourth state is indicating that the CCO is not running

because of IFFHLT/IFFTUNE or a defect. It is possible to route the CCO output signal to the MFO pin for test

purposes and to determining the ratio of the CCO and the filter.

The working principle of the digital tuning circuit is as follows. First the crystal frequency is divided by RIFF

and then by 4. This is the tuning period with which the IFFVAL values can be changed. Now the digital

control counts the positive edges of the CCO output in half of the tuning period. The typical count value for

perfect tuning should be 400. Since the CCO shows phase noise it is necessary to define a certain dead

band in which no tuning takes place. The limits are hardwired in the control logic and can not be changed.

The lower dead band limit is 394 and the upper limit is 407. If the counts of CCO are smaller or larger than

these values then the circuit increases or decreases IFFVAL by one. There is no change of IFFVAL if the

count is inside the dead band.

Unfortunately glitches produced in the digital tuning circuit cause IFFVAL to be decreased even in the dead

band. The glitches appear randomly but about 10 to 20 within one second. This causes the filter to be

pushed towards the lower dead band limit. Once it is reached, IFFVAL will be decreased by 1 for one tuning

period and be immediately increased in the next tuning period since the CCO count is smaller than 394. If

the FSK frequency deviation is smaller than 15kHz and the peak detectors are used, then we recommend

to disable the tuning with IFFHLT=1 during the reception period.

For typical process parameters, at room temperature and for 5V supply voltage the following assumptions

can be made. One LSB of IFFVAL will shift the filter frequency by about 10.2kHz. The demodulator gain at

low gain setting is about 12mV/kHz (leading to 120mV pulses due to the glitches!), one LSB of RIFF will shift

the filter frequency by about 3kHz (reciprocal to RIFF!), one LSB of the CCO count shifts the frequency error

of the filter by about 5kHz. The temperature drift of the filter is about 0.47 IFFVAL steps per Kelvin so the

drift of the filter is about 4.8kHz per Kelvin.

3.3.6. IF Amplifier (IFA)

After passing the IF filter the receiving signal is amplitude limited by means of a high gain limiting amplifier.

Its small signal gain is about 68dB. A received signal strength indicator (RSSI) voltage is generated in the IF

amplifier. It is available at pin RSSI. The voltage at this pin is proportional to the input level of the receiver

(in dB scales). There are two sensitivity settings selectable with RSSIGAIN (see 4.1.2), one with about

39mV/dB and the default setting with about 51mV/dB. By using this RSSI output signal the incoming signal

strength of different transmitters can be determined. The same RSSI signal is used for receiving ASK

modulated signals if MODSEL (see 4.1.6) is HIGH.

The IFA generates two digital signals RSSIL and RSSIH that indicate the level range of the RSSI voltage. If the

level is in the lower quarter of the RSSI voltage range then both signals are LOW. If it is in the upper quarter

of the RSSI range then both signals are HIGH. In between, the RSSIL signal is HIGH and RSSIH is LOW. Both

values can be read out from register R7 of the IC (see 4.1.8). These two signals are also used for the AGC

feature.

MLX71122 Datasheet(PDF) 31 Page - Melexis Microelectronic Systems

MLX71122 Datasheet(HTML) 31 Page - Melexis Microelectronic Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL