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MLX71122 Datasheet(PDF) 30 Page - Melexis Microelectronic Systems |
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MLX71122 Datasheet(HTML) 30 Page - Melexis Microelectronic Systems |
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30 / 59 page ![]() MLX71122 300 to 930MHz FSK/FM/ASK Receiver Datasheet REVISION 014 – AUGUST, 2016 Page 30 of 59 390 10 71122 01 3.3.4. FSK Demodulator FSK reception is turned on if bit MODSEL in register R5 is set to LOW (default). The demodulator is completely internally implemented, so no external, expensive discriminator device is needed. The used FSK demodulator is based on a phase shifter and a mixer as depicted in Fig.14. Fig. 14: Block diagram of FSK demodulator The phase shifter provides a phase shift of 90 degrees to the original IF signal at exactly 2MHz. There is no AFC feature integrated since the frequency acceptance range of the demodulator is wide enough with about ±150kHz. The phase shift is regulated by the same control loop that controls the center frequency of the IF-filter. Tuning of the IF-filter will also change the DC value of the demodulator output. We recommend turning off the tuning during receive mode using IFFHLT (see 4.1.7) if small frequency deviations below ±20kHz have to be detected. The gain of the demodulator can be changed with bit DEMGAIN (see 4.1.1). It can be set to 12mV/kHz (default) or to 14.5mV/kHz. 3.3.5. Autotuning Circuit An auto-tuning mechanism is implemented that permanently adjusts the bias current of the transconductance cells of the IF filter and the FSK demodulator in order to eliminate process, temperature and supply voltage variations. For this purpose a matched master bi-quad is used as oscillator in a current controlled oscillator (CCO) at 3MHz embedded in a PLL structure. A more detailed view on the tuning circuit is shown in Fig.15. RO f CCO digital dead band control ~2.9094MHz IFFVAL tuning signal proportional to frequency D A IF Filter fcenter = 2.0000MHz IFAIN MIX2OUT 8 4 RIFF IFFSTATE[1:0] IFFVAL [7:0] 10 IFFTUNE IFFHLT IFFPRES[7: 0] 10 tune T count CCO cylces in Ttune/2 => N N < 394 => IFFVAL + 1 N > 407 => IFFVAL - 1 default = 684 frequency matching once per Ttune: typ. 10MHz Fig.15: block diagram of digital tuning circuitry IN limiter limiter limiter LP 1st order LP 1st order buffer OUT phase shifter |
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