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MLX71122 Datasheet(PDF) 22 Page - Melexis Microelectronic Systems |
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MLX71122 Datasheet(HTML) 22 Page - Melexis Microelectronic Systems |
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22 / 59 page ![]() MLX71122 300 to 930MHz FSK/FM/ASK Receiver Datasheet REVISION 014 – AUGUST, 2016 Page 22 of 59 390 10 71122 01 List of Mathematical Acronyms A divider ratio of the swallow counter (part of feedback divider) FB f frequency at the feedback divider output (x) floor The floor function gives the largest integer less than or equal to x. For example, floor(5.4) gives 5, floor(-6.3) gives -7. PFD f PFD frequency in locked state R RO f R f reference frequency of the PLL RO f frequency of the crystal reference oscillator VCO f frequency of the VCO (equals the LO1 signal of the first mixer) A P N N tot total divider ratio of the PLL feedback path N divider ratio of the program counter (part of feedback divider) LO2 N LO2DIV divider ratio, to derive the LO2 signal from LO1 (N1 = 4 or 8) P divider ratio of the prescaler (part of feedback divider) R divider ratio of the reference divider R 3.2.1. Pulse Swallow Counter The programmable feedback divider of the PLL is based on a pulse-swallow topology. Fig. 5 depicts its implementation, consisting of a dual-modulus prescaler, an RS latch and two programmable counters. Fig. 5 Pulse Swallow Counter Topology During one cycle of fFB the prescaler begins the operation by dividing by P+1 until the swallow counter A is full. The RS latch is then set and changes the prescaler modulus to P (via the modulus control signal MC) and disables the swallow counter. The division process continues until the program counter N is full and the RS latch is reset. f VCO f P VCO P / P+1 A Program Counter Swallow Counter Modulus Control Signal (MC) Dual Modulus Prescaler f FB PFD N R Q S RS LATCH f FB = f VCO N P + A MC Mode P+1 P 0 1 |
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